Keiji KISHINE

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity
Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA 
Publication:   
Publication Date: 2019/07/01
Vol. E102-C  No. 7  pp. 573-579
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
power integrity, signal integrity, multi-layered inductor, 
 Summary | Full Text:PDF
Burst-Mode CMOS Transimpedance Amplifier Based on a Regulated-Cascode Circuit with Gain-Mode Switching
Takuya KOJIMA Mamoru KUNIEDA Makoto NAKAMURA Daisuke ITO Keiji KISHINE 
Publication:   
Publication Date: 2019/06/01
Vol. E102-A  No. 6  pp. 845-848
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
burst-mode receiver, PON system, transimpedance amplifier, regulated-cascode, 
 Summary | Full Text:PDF
Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System
Takeshi KUBOKI Yusuke OHTOMO Akira TSUCHIYA Keiji KISHINE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/02/01
Vol. E95-A  No. 2  pp. 479-486
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
interwoven inductor, LD driver, optical communication, 
 Summary | Full Text:PDF
Throughput Estimation Method in Burst ACK Scheme for Optimizing Frame Size and Burst Frame Number Appropriate to SNR-Related Error Rate
Shoko OHTERU Keiji KISHINE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/03/01
Vol. E93-B  No. 3  pp. 590-599
Type of Manuscript:  PAPER
Category: Network
Keyword: 
Burst ACK scheme, throughput estimation, 
 Summary | Full Text:PDF
Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks
Kazuhiko TERADA Kenji KAWAI Osamu ISHIDA Keiji KISHINE Noboru IWASAKI Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2005/10/01
Vol. E88-B  No. 10  pp. 3952-3961
Type of Manuscript:  Special Section PAPER (Special Section on Next Generation Photonic Network Technologies)
Category: 
Keyword: 
10 Gbit/s Ethernet, ILS, OAMP, 
 Summary | Full Text:PDF
Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR--
Keiji KISHINE Noboru ISHIHARA Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/04/01
Vol. E84-C  No. 4  pp. 460-469
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock and data recovery, PLL, duplicated loop, low jitter, 2.5-Gb/s, 
 Summary | Full Text:PDF
A Jitter Suppression Technique for a Clock Multiplier
Kiyoshi ISHII Keiji KISHINE Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/04/25
Vol. E83-C  No. 4  pp. 647-651
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock multiplier, phase-locked loop, SAW filter, jitter generation, jitter transfer function, 
 Summary | Full Text:PDF
Low-Power 2.5-Gb/s Si-Bipolar IC Chipset for Optical Receivers and Transmitters Using Low-Voltage and Adjustment-Free Circuit Techniques
Masaki HIROSE Keiji KISHINE Haruhiko ICHINO Noboru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C  No. 3  pp. 511-518
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword: 
optical receiver, optical transmitter, adjustment free, Si bipolar, offset, PLL, 
 Summary | Full Text:PDF