Kazuyuki NAKAMURA


An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O
Hiroyuki MORIMOTO Hiroki KOIKE Kazuyuki NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 945-952
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
3-terminal regulatoradjustablepost fabricationtrimming1-wire serial I/O
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A Realization of Multiple-Output Functions by a Look-Up Table Ring
Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3141-3150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
LUT cascadeLUT ringmultiple-output functionreconfigurable logicprogrammable logic device
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Design Innovations for Multi-Gigahertz-Rate Communication Circuits with Deep-Submicron CMOS Technology
Masakazu KURISU Muneo FUKAISHI Hiroshi ASAZAWA Masato NISHIKAWA Kazuyuki NAKAMURA Michio YOTSUYANAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C  No. 3  pp. 428-437
Type of Manuscript:  INVITED PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: 
Keyword: 
CMOSdeep-submicroncommunicationGigahertz
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PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs
Kazuyuki NAKAMURA Shigeru KUHARA Thoru KIMURA Masahide TAKADA Hisamitsu SUZUKI Hiroshi YOSHIDA Tohru YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 805-811
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
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Logic Functional Level Converter for High Speed Address Decoder of ECL I/O BiCMOS SRAMs
Kazuyuki NAKAMURA Masahide TAKADA Toshio TAKESHIMA Kouichirou FURUTA Tohru YAMAZAKI Kiyotaka IMAI Susumu OHI Yumi SEKINE Yukio MINATO Hisamitsu KIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 845-852
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: SRAM
Keyword: 
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