IEICE Trans

Kazuyoshi TAKAGI

Rapid Single-Flux-Quantum Truncated Multiplier Based on Bit-Level Processing Nobutaka KITO Ryota ODAKA Kazuyoshi TAKAGI
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 607-611 Type of Manuscript: BRIEF PAPER Category: Superconducting Electronics Keyword: rapid single flux quantum circuit, truncated multiplier, pulse logic,
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Algorithms for Evaluating the Matrix Polynomial I+A+A²+…+A^N-1 with Reduced Number of Matrix Multiplications Kotaro MATSUMOTO Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: Publication Date: 2018/02/01 Vol. E101-A No. 2 pp. 467-471 Type of Manuscript: PAPER Category: Algorithms and Data Structures Keyword: evaluation of matrix polynomial, matrix multiplication,
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High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation Masamitsu TANAKA Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/06/01 Vol. E99-C No. 6 pp. 703-709 Type of Manuscript: Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics) Category: Keyword: digital arithmetic, digit-serial processing, hardware algorithm, rapid single-flux-quantum logic, signed-digit representation, systolic array,
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RSFQ 4-bit Bit-Slice Integer Multiplier Guang-Ming TANG Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/06/01 Vol. E99-C No. 6 pp. 697-702 Type of Manuscript: Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics) Category: Keyword: multiplier, single-flux-quantum (SFQ), microprocessor, superconducting integrated circuits,
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A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model Takahiro KAWAGUCHI Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2556-2564 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: single-flux-quantum circuit, static timing analysis, formal verification,
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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis Akihiro SUDA Hideki TAKASE Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2498-2506 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, array partitioning, buffer management, Polyhedral Optimization,
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Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm² Nb Process Xizhu PENG Yuki YAMANASHI Nobuyuki YOSHIKAWA Akira FUJIMAKI Naofumi TAKAGI Kazuyoshi TAKAGI Mutsuo HIDAKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 pp. 188-193 Type of Manuscript: Special Section PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits) Category: Keyword: floating point unit, multiplier, LSRDP, SFQ circuit, superconductive integrated circuit,
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Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors Akira FUJIMAKI Masamitsu TANAKA Ryo KASAGI Katsumi TAKAGI Masakazu OKADA Yuhi HAYAKAWA Kensuke TAKATA Hiroyuki AKAIKE Nobuyuki YOSHIKAWA Shuichi NAGASAWA Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 pp. 157-165 Type of Manuscript: INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits) Category: Keyword: advanced process, cell-based design technique, high-end computing, large-scale integration, rapid single-flux-quantum circuits,
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Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation Shuichi NAGASAWA Kenji HINODE Tetsuro SATOH Mutsuo HIDAKA Hiroyuki AKAIKE Akira FUJIMAKI Nobuyuki YOSHIKAWA Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 pp. 132-140 Type of Manuscript: INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits) Category: Keyword: superconducting fabrication technology, Nb/AlOx/Nb Josephson junction, single flux quantum, planarization, shift register,
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Circuit Description and Design Flow of Superconducting SFQ Logic Circuits Kazuyoshi TAKAGI Nobutaka KITO Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/03/01 Vol. E97-C No. 3 pp. 149-156 Type of Manuscript: INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits) Category: Keyword: single-flux-quantum circuit, design methodology, circuit description, logic design, layout design, design verification,
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A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition Kazuhiro NAKAMURA Ryo SHIMAZAKI Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 456-467 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: speech recognition, hidden Markov model (HMM), VLSI architecture, isolated word recognition,
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Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits Kazuyoshi TAKAGI Yuki ITO Shota TAKESHIMA Masamitsu TANAKA Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/03/01 Vol. E94-C No. 3 pp. 288-295 Type of Manuscript: Special Section PAPER (Special Section on Superconducting Signal Processing Technologies) Category: Keyword: single-flux-quantum circuit, design methodology, clock tree synthesis, clock skew,
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Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm Masamitsu TANAKA Koji OBATA Yuki ITO Shota TAKESHIMA Motoki SATO Kazuyoshi TAKAGI Naofumi TAKAGI Hiroyuki AKAIKE Akira FUJIMAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/04/01 Vol. E93-C No. 4 pp. 435-439 Type of Manuscript: Special Section PAPER (Special Section on Frontiers of Superconductive Electronics) Category: Digital Applications Keyword: single-flux-quantum circuit, computer-aided design, wire router, passive transmission line,
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A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing Kazuhiro NAKAMURA Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/02/01 Vol. E93-D No. 2 pp. 300-305 Type of Manuscript: PAPER Category: VLSI Systems Keyword: speech recognition, hidden Markov model (HMM), VLSI architecture,
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A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3772-3782 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: clock scheduling, clock skew, micropipeline, RSFQ,
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A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/12/01 Vol. E90-C No. 12 pp. 2278-2284 Type of Manuscript: PAPER Category: Superconducting Electronics Keyword: sequential circuit synthesis, one-hot encoding, single-flux-quantum (SFQ),
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Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 pp. 257-266 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic synthesis, dual-rail, RSFQ, binary decision diagrams (BDDs),
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A Hardware Algorithm for Integer Division Using the SD2 Representation Naofumi TAKAGI Shunsuke KADOWAKI Kazuyoshi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/10/01 Vol. E89-A No. 10 pp. 2874-2881 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: computer arithmetic, division, integer division, hardware algorithm, signed-digit representation, VLSI,
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Digit-Recurrence Algorithm for Computing Reciprocal Square-Root Naofumi TAKAGI Daisuke MATSUOKA Kazuyoshi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/01/01 Vol. E86-A No. 1 pp. 221-228 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: computer arithmetic, reciprocal square-root, hardware algorithm, digit-recurrence, computer graphics,
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A VLSI Algorithm for Division in GF(2^m) Based on Extended Binary GCD Algorithm Yasuaki WATANABE Naofumi TAKAGI Kazuyoshi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/05/01 Vol. E85-A No. 5 pp. 994-999 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: finite field arithmetic, division in finite field, hardware algorithm, VLSI algorithm,
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Hardware Synthesis from C Programs with Estimation of Bit Length of Variables Osamu OGAWA Kazuyoshi TAKAGI Yasufumi ITOH Shinji KIMURA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2338-2346 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, hardware/software codesign, VHDL, C language, compiler,
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Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization Kazuyoshi TAKAGI Hiroshi HATAKEDA Shinji KIMURA Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2407-2413 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: Free BDD, Pass-Transistor Logic, Boolean function, logic minimization,
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Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/05/25 Vol. E82-A No. 5 pp. 767-774 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: graph algorithm, minimum cut linear arrangement, VLSI layout, adder tree, multiplier,
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Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-A No. 12 pp. 2515-2520 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Optimization Keyword: timing verification, maximum delay analysis, multiple clock operation, false path,
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Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses Kazuyoshi TAKAGI Koyo NITTA Hironori BOUNO Yasuhiko TAKENAGA Shuzo YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/04/25 Vol. E80-A No. 4 pp. 663-669 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: computational complexity, Boolean function, ordered binary decision diagram, satisfiability, combinational circuit, cutwidth, sum-of-product form, zero-suppressed binary decision diagrams (BDD), ternary decision diagram,
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