|
|
|
|
|
|
|
|
|
|
|
Emerging Memory Solutions for Graphics Applications Katsumi SUIZU Toshiyuki OGAWA Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C
No. 7
pp. 773-781
Type of Manuscript:
INVITED PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: 3D computer graphics, texture mapping, Z-buffer, bandwidth bottleneck, DRAM, system memory, frame buffer, performance comparison, | | Summary | Full Text:PDF(741.6KB) | |
|
A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's Tsukasa OOISHI Mikio ASAKURA Shigeki TOMISHIMA Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C
No. 5
pp. 762-770
Type of Manuscript:
Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
| | Summary | Full Text:PDF(784.8KB) | |
|
|
|
|
|
|
|
|
|
A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 508-515
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
| | Summary | Full Text:PDF(688.1KB) | |
|
A Dual-Mode Sensing Scheme of Capacitor-Coupled EEPROM Cell Masanori HAYASHIKOSHI Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 467-471
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
| | Summary | Full Text:PDF(481.8KB) | |
|
Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM's Mikio ASAKURA Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 495-500
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
| | Summary | Full Text:PDF(552.5KB) | |
|
A Divided/Pausing Bitline Sensing Scheme (DIPS) for ULSI DRAM Core Hideto HIDAKA Yoshio MATSUDA Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E
No. 11
pp. 1852-1854
Type of Manuscript:
Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE) Category: Integrated Circuits Keyword:
| | Summary | Full Text:PDF(158.2KB) | |
|
Mechanism of Bit Line Mode Soft Error for DRAM Mikio ASAKURA Yoshio MATSUDA Katsuhiro TSUKAMOTO Kazuyasu FUJISHIMA Tsutomu YOSHIHARA | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/11/25
Vol. E70-E
No. 11
pp. 1060-1061
Type of Manuscript:
Special Section LETTER (Special Issue: Papers from 1987 National Conference on Semicondutor Devices and Materials IEICE) Category: Semiconductor Devices Keyword:
| | Summary | Full Text:PDF(154.8KB) | |
|