Kazuyasu FUJISHIMA


Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
Hideyuki NODA Kazunari INOUE Hans Jurgen MATTAUSCH Tetsushi KOIDE Katsumi DOSAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Kenji ANAMI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 622-629
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
CMOSTernary CAMnetworkrefresh
 Summary | Full Text:PDF

A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/09/01
Vol. E85-C  No. 9  pp. 1697-1708
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
embedded DRAMsystem on chip3-D graphics concurrent operation
 Summary | Full Text:PDF

A Programmable Geometry Processor with Enhanced Four-Parallel SIMD Type Processing Core for PC-Based 3D Graphics
Hiroyuki KAWAI Yoshitsugu INOUE Junko KOBARA Robert STREITENBERGER Hiroaki SUZUKI Hiroyasu NEGISHI Masatoshi KAMEYAMA Kazunari INOUE Yasutaka HORIBA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/05/01
Vol. E85-C  No. 5  pp. 1200-1210
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
3D graphicsprogrammablegeometrySIMDclip test
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Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
Fukashi MORISHITA Kazutami ARIMOTO Kazuyasu FUJISHIMA Hideyuki OZAKI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 253-259
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SOIfloating bodybody controlhigh speedlow power
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Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's
Yasuo YAMAGUCHI Toshiyuki OASHI Takahisa EIMORI Toshiaki IWAMATSU Shouichi MITAMOTO Katsuhiro SUMA Takahiro TSURUDA Fukashi MORISHITA Masakazu HIROSE Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Yasuo INOUE Tadashi NISHIMURA Hirokazu MIYOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6  pp. 772-780
Type of Manuscript:  INVITED PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
SOLSIMOXDRAMlow-voltage operation
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Emerging Memory Solutions for Graphics Applications
Katsumi SUIZU Toshiyuki OGAWA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 773-781
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
3D computer graphicstexture mappingZ-bufferbandwidth bottleneckDRAMsystem memoryframe bufferperformance comparison
 Summary | Full Text:PDF

A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's
Tsukasa OOISHI Mikio ASAKURA Shigeki TOMISHIMA Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 762-770
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF

A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories
Masaki TSUKUDA Kazutami ARIMOTO Mikio ASAKURA Hideto HIDAKA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1589-1594
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
reduction of design TATdesign methodologyULSI memory
 Summary | Full Text:PDF

A Line-Mode Test with Data Register for ULSI Memory Architecture
Tsukasa OOISHI Masaki TSUKUDE Kazutani ARIMOTO Yoshio MATSUDA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1595-1603
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
line-mode testdata inversion registermain-sub I/O line architecture
 Summary | Full Text:PDF

A ST (Stretchable Memory Matrix) DRAM with Multi-Valued Addressing Scheme
Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11  pp. 1323-1332
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
multi-valued addressing scheme
 Summary | Full Text:PDF

A New Array Architecture for 16 Mb DRAMs with Special Page Mode
Masaki TSUKUDE Tsukasa OISHI Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10  pp. 1267-1274
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
array architecturedynamic memoryhigh speed accesswide operating marginlow power dissipation
 Summary | Full Text:PDF

A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's
Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 508-515
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF

A Dual-Mode Sensing Scheme of Capacitor-Coupled EEPROM Cell
Masanori HAYASHIKOSHI Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 467-471
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF

Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM's
Mikio ASAKURA Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 495-500
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF

A Divided/Pausing Bitline Sensing Scheme (DIPS) for ULSI DRAM Core
Hideto HIDAKA Yoshio MATSUDA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/11/25
Vol. E73-E  No. 11  pp. 1852-1854
Type of Manuscript:  Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 
 Summary | Full Text:PDF

Mechanism of Bit Line Mode Soft Error for DRAM
Mikio ASAKURA Yoshio MATSUDA Katsuhiro TSUKAMOTO Kazuyasu FUJISHIMA Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/11/25
Vol. E70-E  No. 11  pp. 1060-1061
Type of Manuscript:  Special Section LETTER (Special Issue: Papers from 1987 National Conference on Semicondutor Devices and Materials IEICE)
Category: Semiconductor Devices
Keyword: 
 Summary | Full Text:PDF