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A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's Tsukasa OOISHI Mikio ASAKURA Shigeki TOMISHIMA Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C
No. 5
pp. 762-770
Type of Manuscript:
Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994)) Category: Keyword:
| | Summary | Full Text:PDF(784.8KB) | |
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Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM's Mikio ASAKURA Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 495-500
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
| | Summary | Full Text:PDF(552.5KB) | |
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A Dual-Mode Sensing Scheme of Capacitor-Coupled EEPROM Cell Masanori HAYASHIKOSHI Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 467-471
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
| | Summary | Full Text:PDF(481.8KB) | |
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A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 508-515
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium) Category: Keyword:
| | Summary | Full Text:PDF(688.1KB) | |
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