Kazunori OHUCHI


Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4  pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMcascadeNANDfolded bitlineopen bitlinedie sizenoise immunity
 Summary | Full Text:PDF(803.3KB)

An Ultra Low Voltage SOI CMOS Pass-Gate Logic
Tsuneaki FUSE Yukihito OOWAKI Mamoru TERAUCHI Shigeyoshi WATANABE Makoto YOSHIMI Kazunori OHUCHI Jun'ichi MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3  pp. 472-477
Type of Manuscript:  Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: 
Keyword: 
SOI0.5 V operationultra low voltagepass-gate logicbody-bias control
 Summary | Full Text:PDF(545.6KB)

A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAMpower dissipationreliabilitybit-linewordlinesmall swingthreshold voltagesense amplifiermemory cell
 Summary | Full Text:PDF(772.8KB)

New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
Yukihito OOWAKI Keiji MABUCHI Shigeyoshi WATANABE Kazunori OHUCHI Jun'ichi MATSUNAGA Fujio MASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 845-851
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
α-particlesoft errorDRAM
 Summary | Full Text:PDF(605.2KB)

Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's
Daisaburo TAKASHIMA Shigeyoshi WATANABE Hiroaki NAKANO Yukihito OOWAKI Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 869-872
Type of Manuscript:  Special Section LETTER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF(369.1KB)

Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory
Daisaburo TAKASHIMA Shigeyoshi WATANABE Hiroaki NAKANO Yukihito OOWAKI Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C  No. 5  pp. 771-777
Type of Manuscript:  Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category: 
Keyword: 
 Summary | Full Text:PDF(544.7KB)

Word-Line Architecture for Highly Reliable 64-Mb DRAM
Daisaburo TAKASHIMA Yukihito OOWAKI Ryu OGIWARA Yohji WATANABE Kenji TSUCHIDA Masako OHTA Hiroaki NAKANO Shigeyoshi WATANABE Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C  No. 4  pp. 501-507
Type of Manuscript:  Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category: 
Keyword: 
 Summary | Full Text:PDF(680.9KB)