Kazumi HATAYAMA


Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
Kohei MIYASE Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Yuta YAMATO Hiroshi FURUKAWA Xiaoqing WEN Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/06/01
Vol. E94-D  No. 6  pp. 1216-1226
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
ATPGX-bitX-identificationX-filling
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A Study of Capture-Safe Test Generation Flow for At-Speed Testing
Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7  pp. 1309-1318
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
at-speed scan testingtest generationX-bit identificationX-fillingcapture-safety checking
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FOREWORD
Kazumi HATAYAMA Tsuyoshi SHINOGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1  pp. 1-1
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
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Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs
Kazumi HATAYAMA Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Yasuo SATO Takaharu NAGUMO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3318-3323
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
BISTtest pattern generatorneighborhood patternLFSRreseeding
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DFT Timing Design Methodology for Logic BIST
Yasuo SATO Motoyuki SATO Koki TSUTSUMIDA Kazumi HATAYAMA Kazuyuki NOMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3049-3055
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
DFTat-speed BISTtiming designmultiple-clock
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High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model
Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
delay testingpath selectionfault simulationtest generationpath-status graph
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Deterministic Built-in Test with Neighborhood Pattern Generator
Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/05/01
Vol. E85-D  No. 5  pp. 874-883
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
BISTtest pattern generatorreseedingbit-flippingseed generation
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On Acceleration of Test Points Selection for Scan-Based BIST
Michinobu NAKAO Kazumi HATAYAMA Isao HIGASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7  pp. 668-674
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Built-in Self-Test
Keyword: 
test pointsBISToptimizationtestability
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