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| Kazuhito ITO
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Energy Minimization of Double Modular Redundant Conditional Processing by Common Condition Dependency
Kazuhito ITO | Publication:
Publication Date: 2020/04/01
Vol. E103-C
No. 4
pp. 181-185
Type of Manuscript:
BRIEF PAPER
Category: Integrated Electronics
Keyword:
DMR, conditional operation, ILP, | | | Summary | Full Text:PDF | |
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Hardware-Efficient Local Extrema Detection for Scale-Space Extrema Detection in SIFT Algorithm
Kazuhito ITO Hiroki HAYASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A
No. 12
pp. 2507-2510
Type of Manuscript:
Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
SIFT, local extrema detection, scale-space extrema detection, | | | Summary | Full Text:PDF | |
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A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining
Kazuhito ITO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/05/01
Vol. E98-A
No. 5
pp. 1058-1066
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
Reed-Solomon code, syndrome key equation solution, low power, folding, | | | Summary | Full Text:PDF | |
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Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage
Kazuhito ITO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A
No. 12
pp. 2530-2539
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
triple modular redundancy, low energy, MIP, simulated annealing, schedule exploration, | | | Summary | Full Text:PDF | |
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Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders
Kazuhito ITO Ryoto SHIRASAKA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A
No. 12
pp. 2680-2688
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
Viterbi decoding, convolutional code, look-ahead computation, high throughput, | | | Summary | Full Text:PDF | |
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Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors
Kazuhito ITO Takuya NUMATA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C
No. 4
pp. 463-472
Type of Manuscript:
Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category:
Keyword:
low power, functional unit, narrow operand, | | | Summary | Full Text:PDF | |
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A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes
Kazuhito ITO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/04/01
Vol. E95-A
No. 4
pp. 767-775
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
Viterbi decoder, convolutional code, trace back, survivor memory, low power, | | | Summary | Full Text:PDF | |
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A Processor Accelerator for Software Decoding of BCH Codes
Kazuhito ITO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A
No. 7
pp. 1329-1337
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
error correction code, BCH, accelerator, pipelining, | | | Summary | Full Text:PDF | |
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