Kazuhito ITO


Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution
Kazuhito ITO Yuto ISHIHARA Shinichi NISHIZAWA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2271-2279
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
soft errorerror detectionDMRcheckpointscheduling
 Summary | Full Text:PDF

Hardware-Efficient Local Extrema Detection for Scale-Space Extrema Detection in SIFT Algorithm
Kazuhito ITO Hiroki HAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2507-2510
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
SIFTlocal extrema detectionscale-space extrema detection
 Summary | Full Text:PDF

Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2453-2462
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Reed-Solomon codekey equation solverEuclidean algorithmpipelined recursive KES
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A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/05/01
Vol. E98-A  No. 5  pp. 1058-1066
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Reed-Solomon codesyndrome key equation solutionlow powerfolding
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Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12  pp. 2530-2539
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
triple modular redundancylow energyMIPsimulated annealingschedule exploration
 Summary | Full Text:PDF

Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders
Kazuhito ITO Ryoto SHIRASAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12  pp. 2680-2688
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
Viterbi decodingconvolutional codelook-ahead computationhigh throughput
 Summary | Full Text:PDF

Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors
Kazuhito ITO Takuya NUMATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4  pp. 463-472
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low powerfunctional unitnarrow operand
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An Area-Time Efficient Key Equation Solver with Euclidean Algorithm for Reed-Solomon Decoders
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/02/01
Vol. E96-A  No. 2  pp. 609-617
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
error correctionReed-Solomon codeReed-Solomon decoderkey equation solution
 Summary | Full Text:PDF

A Processor Accelerator for Software Decoding of Reed-Solomon Codes
Kazuhito ITO Keisuke NASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/05/01
Vol. E95-A  No. 5  pp. 884-893
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
error correction codeReed-Solomonacceleratordecoding
 Summary | Full Text:PDF

A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/04/01
Vol. E95-A  No. 4  pp. 767-775
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Viterbi decoderconvolutional codetrace backsurvivor memorylow power
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A Processor Accelerator for Software Decoding of BCH Codes
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7  pp. 1329-1337
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
error correction codeBCHacceleratorpipelining
 Summary | Full Text:PDF

New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec
Trio ADIONO Tsuyoshi ISSHIKI Chawalit HONSAWEK Kazuhito ITO Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6  pp. 1396-1407
Type of Manuscript:  PAPER
Category: Image
Keyword: 
H.263+rate controloptimum bit allocationlow encoder-decoder delaylip synchronization
 Summary | Full Text:PDF

System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications
Chawalit HONSAWEK Kazuhito ITO Tomohiko OHTSUKA Trio ADIONO Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11  pp. 2614-2622
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
system-MSPALSI designvideotelephony applicationsH.263+ ITU standard
 Summary | Full Text:PDF

An Overlapped Scheduling Method for an Iterative Processing Algorithm with Conditional Operations
Kazuhito ITO Tatsuya KAWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/03/25
Vol. E81-A  No. 3  pp. 429-438
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
schedulinghigh-level synthesisdigital signal processingconditional branchoverlapped schedule
 Summary | Full Text:PDF

Bits Truncation Adapteve Pyramid Algorithm for Motion Estimation of MPEG2
Li JIANG Kazuhito ITO Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/08/25
Vol. E80-A  No. 8  pp. 1438-1445
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
bits truncationadaptivepyramidmotion estimationMPEG2
 Summary | Full Text:PDF

Modularization and Processor Placement for DSP Neo-Systolic Array
Kazuhito ITO Kesami HAGIWARA Takashi SHIMIZU Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3  pp. 349-361
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
VLSI system compilerVLSI signal processingneo-systolic array
 Summary | Full Text:PDF