Kazuhiro NOMURA


EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout
Kazuhiro NOMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1564-1570
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: EB Tester
Keyword: 
EB testerline delay faultfault localizationlayout analysiscombinational circuits
 Summary | Full Text:PDF(296.4KB)