IEICE Trans

Kazuhiko IWASAKI

Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering Masayuki ARAI Shingo INUYAMA Kazuhiko IWASAKI
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 pp. 2262-2270 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: weighted fault coverage, critical area, critical area analysis, bridge fault, open fault,
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Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage Masayuki ARAI Kazuhiko IWASAKI
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1488-1495 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: weighted fault coverage, critical area, test cost reduction, test pattern reduction, bridge fault, open fault,
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Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints Ryo SUZUKI Mamoru OHARA Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/01/01 Vol. E96-D No. 1 pp. 141-145 Type of Manuscript: LETTER Category: Dependable Computing Keyword: distributed checkpointing, hybrid state saving, checkpoint-space reclamation, time arrangement rotation,
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Reduction of Area per Good Die for SoC Memory Built-In Self-Test Masayuki ARAI Tatsuro ENDO Kazuhiko IWASAKI Michinobu NAKAO Iwao SUZUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2463-2471 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: memory BIST, BISR, embedded SRAM, area per good die, iterative improvement algorithm,
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Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression Anis UZZAMAN Brion KELLER Brian FOUTZ Sandeep BHATIA Thomas BARTENSTEIN Masayuki ARAI Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/01/01 Vol. E93-D No. 1 pp. 17-23 Type of Manuscript: Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs) Category: Keyword: test compression, hybrid compression, volume diagnosis, ATPG, partial good chip,
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Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI Tatsuru MATSUO Takahisa HIRAIDE Hideaki KONISHI Michiaki EMORI Takashi AIKYO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 726-735 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Test Compression Keyword: test data compression, test response compaction, BIST-aided scan test, X-value, ATPG,
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Study on Test Data Reduction Combining Illinois Scan and Bit Flipping Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 720-725 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Test Compression Keyword: test data reduction, Illinois scan, bit flipping, BIST-aided scan test,
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Study on Expansion of Convolutional Compactors over Galois Field Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 706-712 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Test Compression Keyword: convolutional compactor, test response compaction, X-masking, galois field,
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Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks Mamoru OHARA Ryo SUZUKI Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/09/01 Vol. E89-A No. 9 pp. 2386-2395 Type of Manuscript: PAPER Category: Reliability, Maintainability and Safety Analysis Keyword: reliability, distributed systems, hybrid state saving Time Warp simulation, evaluation model,
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Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 1047-1054 Type of Manuscript: PAPER Category: Reliability, Maintainability and Safety Analysis Keyword: reliability analysis, evaluation model, convolutional code, packet loss, forward error correction, packet buffer size,
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Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration Yasuo SATO Iwao YAMAZAKI Hiroki YAMANAKA Toshio IKEDA Masahiro TAKAKURA Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/09/01 Vol. E87-D No. 9 pp. 2179-2185 Type of Manuscript: PAPER Category: Dependable Computing Keyword: diagnosis, open fault, coupling effect,
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Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 586-591 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Scan Testing Keyword: hybrid BIST, n-detection test, partially rotational scan, low-speed tester,
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Seed Selection Procedure for LFSR-Based Random Pattern Generators Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3063-3071 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: BIST, LFSR, test-per-clock, test-per-scan, seed, polynomial,
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A Technique for Constructing Dependable Internet Server Cluster Mamoru OHARA Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 pp. 2198-2208 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: server clustering, distributed algorithm, IP multicast, DNS, dependability evaluation,
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High-Assurance Video Conference System over the Internet Masayuki ARAI Hitoshi KUROSU Mamoru OHARA Ryo SUZUKI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2003/10/01 Vol. E86-B No. 10 pp. 2940-2947 Type of Manuscript: Special Section PAPER (IEICE/IEEE Joint Special Issue on Assurance Systems and Networks) Category: Network Systems and Applications Keyword: video conference system, convolutional codes, H.323, Xcast, packet loss,
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High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1506-1514 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Test and Diagnosis for Timing Faults Keyword: delay testing, path selection, fault simulation, test generation, path-status graph,
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Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan Kenichi ICHINO Takeshi ASAKAWA Satoshi FUKUMOTO Kazuhiko IWASAKI Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1490-1497 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: BIST Keyword: hybrid BIST, unmodeled fault, n-detection test, partially rotational scan, at-speed testing,
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Deterministic Built-in Test with Neighborhood Pattern Generator Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/05/01 Vol. E85-D No. 5 pp. 874-883 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: BIST, test pattern generator, reseeding, bit-flipping, seed generation,
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Analytical Evaluation of Internet Packet Loss Recovery Using Convolutional Codes Anna YAMAGUCHI Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/05/01 Vol. E85-D No. 5 pp. 854-863 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: fault tolerance, Internet packet loss, convolutional code, loss recovery, post-reconstruction receiving rate,
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Fault-Tolerance Design for Multicast Using Convolutional-Code-Based FEC and Its Analytical Evaluation Anna YAMAGUCHI Masayuki ARAI Hitoshi KUROSU Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/05/01 Vol. E85-D No. 5 pp. 864-873 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: fault tolerance, multicast, Internet packet loss, punctured convolutional codes, loss recovery,
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Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults Kazuhiko IWASAKI Hiroyuki GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-A No. 5 pp. 885-888 Type of Manuscript: Special Section LETTER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: BIST, test length, random-pattern-resistant fault, LFSR, integer partition problem,
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Mesh Spiral and Mesh Random Networks Kazuhiko IWASAKI Akinori FURUTA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/08/25 Vol. E79-D No. 8 pp. 1093-1098 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Interconnection Networks Keyword: interconnection network, mesh spiral network, mesh random network, diameter, average distance,
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Analysis of Aliasing Probability for MISRs by Using Complete Weight Distributions Kazuhiko IWASAKI Sandeep K. GUPTA Prawat NAGVAJARA Tadao KASAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/25 Vol. E78-A No. 12 pp. 1691-1698 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: BIST, aliasing probability, error-correcting codes, complete weight distribution,
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Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs Kazuhiko IWASAKI Shou-Ping FENG Toru FUJIWARA Tadao KASAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/11/25 Vol. E75-D No. 6 pp. 835-841 Type of Manuscript: Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems) Category: Keyword: BIST, aliasing probability, multiple MISR, M-stage MISR with m imputs, binary symmetric channel,
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Coding Theory Applications in Fault Tolerant Computing Yoshihiro IWADARE Eiji FUJIWARA Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/02/25 Vol. E74-A No. 2 pp. 244-258 Type of Manuscript: INVITED PAPER Category: Keyword:
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