Kazuhiko IWASAKI


Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering
Masayuki ARAI Shingo INUYAMA Kazuhiko IWASAKI 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12  pp. 2262-2270
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
weighted fault coveragecritical areacritical area analysisbridge faultopen fault
 Summary | Full Text:PDF

Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage
Masayuki ARAI Kazuhiko IWASAKI 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1488-1495
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
weighted fault coveragecritical areatest cost reductiontest pattern reductionbridge faultopen fault
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Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints
Ryo SUZUKI Mamoru OHARA Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/01/01
Vol. E96-D  No. 1  pp. 141-145
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
distributed checkpointinghybrid state savingcheckpoint-space reclamationtime arrangement rotation
 Summary | Full Text:PDF

Reduction of Area per Good Die for SoC Memory Built-In Self-Test
Masayuki ARAI Tatsuro ENDO Kazuhiko IWASAKI Michinobu NAKAO Iwao SUZUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2463-2471
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
memory BISTBISRembedded SRAMarea per good dieiterative improvement algorithm
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Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression
Anis UZZAMAN Brion KELLER Brian FOUTZ Sandeep BHATIA Thomas BARTENSTEIN Masayuki ARAI Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1  pp. 17-23
Type of Manuscript:  Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category: 
Keyword: 
test compressionhybrid compressionvolume diagnosisATPGpartial good chip
 Summary | Full Text:PDF

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate
Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI Tatsuru MATSUO Takahisa HIRAIDE Hideaki KONISHI Michiaki EMORI Takashi AIKYO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 726-735
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Test Compression
Keyword: 
test data compressiontest response compactionBIST-aided scan testX-valueATPG
 Summary | Full Text:PDF

Study on Test Data Reduction Combining Illinois Scan and Bit Flipping
Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 720-725
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Test Compression
Keyword: 
test data reductionIllinois scanbit flippingBIST-aided scan test
 Summary | Full Text:PDF

Study on Expansion of Convolutional Compactors over Galois Field
Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 706-712
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Test Compression
Keyword: 
convolutional compactortest response compactionX-maskinggalois field
 Summary | Full Text:PDF

Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks
Mamoru OHARA Ryo SUZUKI Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/09/01
Vol. E89-A  No. 9  pp. 2386-2395
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
reliabilitydistributed systemshybrid state saving Time Warp simulationevaluation model
 Summary | Full Text:PDF

Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size
Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 1047-1054
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
reliability analysisevaluation modelconvolutional codepacket lossforward error correctionpacket buffer size
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Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration
Yasuo SATO Iwao YAMAZAKI Hiroki YAMANAKA Toshio IKEDA Masahiro TAKAKURA Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/09/01
Vol. E87-D  No. 9  pp. 2179-2185
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
diagnosisopen faultcoupling effect
 Summary | Full Text:PDF

Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits
Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3  pp. 586-591
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Scan Testing
Keyword: 
hybrid BISTn-detection testpartially rotational scanlow-speed tester
 Summary | Full Text:PDF

Seed Selection Procedure for LFSR-Based Random Pattern Generators
Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3063-3071
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
BISTLFSRtest-per-clocktest-per-scanseedpolynomial
 Summary | Full Text:PDF

A Technique for Constructing Dependable Internet Server Cluster
Mamoru OHARA Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10  pp. 2198-2208
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
server clusteringdistributed algorithmIP multicastDNSdependability evaluation
 Summary | Full Text:PDF

High-Assurance Video Conference System over the Internet
Masayuki ARAI Hitoshi KUROSU Mamoru OHARA Ryo SUZUKI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/10/01
Vol. E86-B  No. 10  pp. 2940-2947
Type of Manuscript:  Special Section PAPER (IEICE/IEEE Joint Special Issue on Assurance Systems and Networks)
Category: Network Systems and Applications
Keyword: 
video conference systemconvolutional codesH.323Xcastpacket loss
 Summary | Full Text:PDF

High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model
Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
delay testingpath selectionfault simulationtest generationpath-status graph
 Summary | Full Text:PDF

Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan
Kenichi ICHINO Takeshi ASAKAWA Satoshi FUKUMOTO Kazuhiko IWASAKI Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1490-1497
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: BIST
Keyword: 
hybrid BISTunmodeled faultn-detection testpartially rotational scanat-speed testing
 Summary | Full Text:PDF

Deterministic Built-in Test with Neighborhood Pattern Generator
Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/05/01
Vol. E85-D  No. 5  pp. 874-883
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
BISTtest pattern generatorreseedingbit-flippingseed generation
 Summary | Full Text:PDF

Analytical Evaluation of Internet Packet Loss Recovery Using Convolutional Codes
Anna YAMAGUCHI Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/05/01
Vol. E85-D  No. 5  pp. 854-863
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
fault toleranceInternet packet lossconvolutional codeloss recoverypost-reconstruction receiving rate
 Summary | Full Text:PDF

Fault-Tolerance Design for Multicast Using Convolutional-Code-Based FEC and Its Analytical Evaluation
Anna YAMAGUCHI Masayuki ARAI Hitoshi KUROSU Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/05/01
Vol. E85-D  No. 5  pp. 864-873
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
fault tolerancemulticastInternet packet losspunctured convolutional codesloss recovery
 Summary | Full Text:PDF

Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults
Kazuhiko IWASAKI Hiroyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5  pp. 885-888
Type of Manuscript:  Special Section LETTER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
BISTtest lengthrandom-pattern-resistant faultLFSRinteger partition problem
 Summary | Full Text:PDF

Mesh Spiral and Mesh Random Networks
Kazuhiko IWASAKI Akinori FURUTA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1093-1098
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
interconnection networkmesh spiral networkmesh random networkdiameteraverage distance
 Summary | Full Text:PDF

Analysis of Aliasing Probability for MISRs by Using Complete Weight Distributions
Kazuhiko IWASAKI Sandeep K. GUPTA Prawat NAGVAJARA Tadao KASAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12  pp. 1691-1698
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
BISTaliasing probabilityerror-correcting codescomplete weight distribution
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Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs
Kazuhiko IWASAKI Shou-Ping FENG Toru FUJIWARA Tadao KASAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6  pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
BISTaliasing probabilitymultiple MISRM-stage MISR with m imputsbinary symmetric channel
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Coding Theory Applications in Fault Tolerant Computing
Yoshihiro IWADARE Eiji FUJIWARA Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/02/25
Vol. E74-A  No. 2  pp. 244-258
Type of Manuscript:  INVITED PAPER
Category: 
Keyword: 
 Summary | Full Text:PDF