IEICE Trans

Kazuharu YAMATO

On a Weight Limit Approach for Enhancing Fault Tolerance of Feedforward Neural Networks Naotake KAMIURA Teijiro ISOKAWA Yutaka HATA Nobuyuki MATSUI Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/11/25 Vol. E83-D No. 11 pp. 1931-1939 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: feedforward neural networks, fault tolerance, backpropagation algorithm, stuck-at faults, generalization ability,
	Summary \| Full Text:PDF

Design of Multiple-Valued Programmable Logic Array with Unary Function Generators Yutaka HATA Naotake KAMIURA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/09/25 Vol. E82-D No. 9 pp. 1254-1260 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, programmable logic array, unary function, logic design, minimization,
	Summary \| Full Text:PDF

Design and Fault Masking of Two-Level Cellular Arrays on Multiple-Valued Logic Naotake KAMIURA Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/25 Vol. E79-D No. 10 pp. 1453-1461 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: multiple-valued logic, fault masking, cellular array and switch cell,
	Summary \| Full Text:PDF

Minimization of Multiple-Valued Logic Expressions with Kleenean Coefficients Yutaka HATA Takahiro HOZUMI Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/03/25 Vol. E79-D No. 3 pp. 189-195 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, minimization, Kleenean functions, two-level realization, sum-of-products expression,
	Summary \| Full Text:PDF

Interpolation Technique of Fingerprint Features for Personal Verification Kazuharu YAMATO Toshihide ASADA Yutaka HATA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/11/25 Vol. E77-D No. 11 pp. 1306-1309 Type of Manuscript: Special Section LETTER (Special Issue on Computer Vision) Category: Keyword: interpolation technique, fingerprint identification, low-quality image, histogram equalization, directional Laplacian filter,
	Summary \| Full Text:PDF

Design of Repairable Cellular Arrays on Multiple-Valued Logic Naotake KAMIURA Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/08/25 Vol. E77-D No. 8 pp. 877-884 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: multiple-valued logic, ecllular array, fault diagnosis, repair, design for testability,
	Summary \| Full Text:PDF

On a Class of Multiple-Valued Logic Functions with Truncated Sum, Differential Product and Not Operations Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/05/25 Vol. E77-D No. 5 pp. 567-573 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: computer hardware and design, multiple-valued logic, truncated sum, completeness, number of the logic functions,
	Summary \| Full Text:PDF

Output Permutation and the Maximum Number of Implicants Needed to Cover the Multiple-Valued Logic Functions Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/25 Vol. E76-D No. 5 pp. 555-561 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Logic Design Keyword: computer hardware and design, multiple-valued some-of-products expressions, optimal output permutation, logic complexity, upper bounds,
	Summary \| Full Text:PDF

Design of a Multiple-Valued Cellular Array Naotake KAMIURA Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/25 Vol. E76-C No. 3 pp. 412-418 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: integrated electronics, multiple-valued logic circuit, combinational switching functions, two-dimensional cellular arrays, switching cell,
	Summary \| Full Text:PDF

Automatic Fingerprint Classifier and Its Application to Access Control Satoshi HASHIMOTO Yutaka HATA Kyoichi NAKASHIMA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1990/07/25 Vol. E73-E No. 7 pp. 1120-1126 Type of Manuscript: Special Section PAPER (Special Issue on Cryptography and Information Security) Category: Applications Keyword:
	Summary \| Full Text:PDF

A Necessary and Sufficient Condition for m-Valued Majority Functions Yutaka HATA Kyoichi NAKASHIMA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/08/25 Vol. E70-E No. 8 pp. 715-718 Type of Manuscript: LETTER Category: Automaton, Language and Theory of Computing Keyword:
	Summary \| Full Text:PDF

Testing and Realization of Three-Valued Majority Functions by Complete Monotonicity Kazuharu YAMATO Kyoichi NAKASHIMA Yutaka HATA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1986/08/25 Vol. E69-E No. 8 pp. 852-858 Type of Manuscript: PAPER Category: Computer System Keyword:
	Summary \| Full Text:PDF

Synthesis Method of Incompletely Specified Ternary Function Based on Some Polyphecks Kazuharu YAMATO Kyoichi NAKASHIMA Yoshiaki MIYOSHI Naohiro FUKUDA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1984/03/25 Vol. E67-E No. 3 pp. 166-167 Type of Manuscript: LETTER Category: Multi-Valued Logic Keyword:
	Summary \| Full Text:PDF

Some Properties of Multi-State Monotone Systems and Their Boolean Structure Functions Kyoichi NAKASHIMA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1983/09/25 Vol. E66-E No. 9 pp. 535-542 Type of Manuscript: PAPER Category: System Reliability Keyword:
	Summary \| Full Text:PDF

Synthesis Method for Ternary Logic Function Based on NOR-Type Polypheck Michiaki YANAGITA Yoshiaki MIYOSHI Kyoichi NAKASHIMA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1983/05/25 Vol. E66-E No. 5 pp. 313-320 Type of Manuscript: PAPER Category: Automata and Languages Keyword:
	Summary \| Full Text:PDF

Methods for Determining Failure-Data Collection Scheme of System Components by Bayesian Technique Kyoichi NAKASHIMA Kazuharu YAMATO Tsuyoshi KAMADA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1982/04/25 Vol. E65-E No. 4 pp. 194-201 Type of Manuscript: PAPER Category: Miscellaneous Keyword:
	Summary \| Full Text:PDF