Katsutaka KIMURA


Trends in High-Density Flash Memory Technologies
Takashi KOBAYASHI Hideaki KURATA Katsutaka KIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/10/01
Vol. E87-C  No. 10  pp. 1656-1663
Type of Manuscript:  Special Section PAPER (Special Section on New Era of Nonvolatile Memories)
Category: Flash Memory
Keyword: 
flash memoryhigh densityAG-ANDmultilevelhigh-speed programming
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A High-Endurance Read/Write Scheme for Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
Hiroki FUJISAWA Takeshi SAKATA Tomonori SEKIGUCHI Kazuyoshi TORII Katsutaka KIMURA Kazuhiko KAJIGAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6  pp. 763-770
Type of Manuscript:  Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: FeRAMs
Keyword: 
DRAMferroelectric memoryhigh speedlow-powerhigh-endurance
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Programming and Program-Verification Methods for Low-Voltage Flash Memories Using a Sector Programming Scheme
Katsutaka KIMURA Toshihiro TANAKA Masataka KATO Tetsuo ADACHI Keisuke OGURA Hitoshi KUME 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 832-837
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memoryprogrameraseFowler-Nordheim tunnelingsector
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Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment
Takayuki KAWAHARA Masakazu AOKI Katsutaka KIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4  pp. 404-413
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
Keyword: 
dynamic terminationtransmission linelow-powerhigh-speed
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The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
Takao WATANABE Masakazu AOKI Katsutaka KIMURA Takeshi SAKATA Kiyoo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1206-1214
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
DRAM-based neuro-chip106-synapse neural network1.5-V digital chip0.5-µm CMOS design rule
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