Katsunori TANAKA


Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
Kohei HOSOKAWA Katsunori TANAKA Yuichi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2810-2817
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
FPGA-based hardware emulatorsSDRAMmemory controllerclock generator
 Summary | Full Text:PDF(907.9KB)

SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits
Katsunori TANAKA Shigeru YAMASHITA Yahiko KAMBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4  pp. 1038-1046
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic designset of pairs of functions to be distinguished (SPFD)look-up-table-based (LUT-based) field programmable gate array (FPGA)SPFD-based effective wire addition
 Summary | Full Text:PDF(265.4KB)

Super-Set of Permissible Functions and Its Application to the Transduction Method
Katsunori TANAKA Yahiko KAMBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3124-3133
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic optimizationpermissible function (PF)transduction methodCSPFMSPFsuper-set of permissible functions (SSPF)
 Summary | Full Text:PDF(377.6KB)