Katsuhiro NORISUE


An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors
Yasuhisa SHIMAZAKI Katsuhiro NORISUE Koichiro ISHIBASHI Hideo MAEJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1693-1698
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
RISC microprocessorcache memorylow power
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