Katsuhiko SHIMABUKURO


Architecture of a Parallel Multiple-Valued Arithmetic VLSI Processor Using Adder-Based Processing Elements
Katsuhiko SHIMABUKURO Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3  pp. 463-471
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
fine-grain parallel processingsigned-digit arithmetic systemmultiple-valued circuit technologybidirectional current-mode circuits
 Summary | Full Text:PDF

Design of a Multiple-Valued VLSI Processor for Digital Control
Katsuhiko SHIMABUKURO Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/09/25
Vol. E75-D  No. 5  pp. 709-717
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
parallel-structure-based VLSI processorsigned-digit arithmetic systemmultiple-valued circuit technologybidirectional current-mode circuits
 Summary | Full Text:PDF