Katsuhiko DEGAWA

A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
Hiroshi INOKAWA Yasuo TAKAHASHI Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1818-1826
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistor (SET), multiple-valued logic (MVL), counter, analytical model, SPICE, 
 Summary | Full Text:PDF
A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic
Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1827-1836
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistors, multiple-valued logic, quantum devices, logic circuits, parallel counters, 
 Summary | Full Text:PDF
Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8  pp. 2001-2010
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
multiple-valued logic, signal processor, FPGAs, FIR filters, 
 Summary | Full Text:PDF