Kan TAKEUCHI


Investigations of Optimum Tier Architectures for ASICs
Kan TAKEUCHI Kazumasa YANAGISAWA Kazuko SAKAMOTO Teruya TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/11/01
Vol. E87-A  No. 11  pp. 2983-2989
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
packing efficiencyinterconnectRent's ruleASICs
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Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
Kan TAKEUCHI Katsumi MATSUNO Yoshinobu NAKAGOME Masakazu AOKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2  pp. 234-242
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
ferroelectric memoryDRAMhalf-V cc platenonvolatile memory
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Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's
Yoshinobu NAKAGOME Kiyoo ITOH Masanori ISODA Kan TAKEUCHI Masakazu AOKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 754-759
Type of Manuscript:  Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category: 
Keyword: 
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