Junpei INOUE


Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model
Hidenari NAKASHIMA Junpei INOUE Kenichi OKADA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3358-3366
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
interconnectlayout compactionphysical designplacementcore utilization
 Summary | Full Text:PDF

Wire Length Distribution Model for System LSI
Takanori KYOGOKU Junpei INOUE Hidenari NAKASHIMA Takumi UEZONO Kenichi OKADA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3445-3452
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
wire length distributioncore utilizationSoClayout-area allocation
 Summary | Full Text:PDF

Evaluation of X Architecture Using Interconnect Length Distribution
Hidenari NAKASHIMA Naohiro TAKAGI Junpei INOUE Kenichi OKADA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3437-3444
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
X architectureinterconnect length distributionILDRent's ruleall-directional interconnect
 Summary | Full Text:PDF