Junichi AKITA

Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade
Junichi AKITA Hiroaki TAKAGI Keisuke DOUMAE Akio KITAGAWA Masashi TODA Takeshi NAGASAKI Toshio KAWASHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10  pp. 1869-1875
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Image Sensor/Vision Chip
Keyword: 
line-of-sight (LoS), saccade, vision chip, column-parallel processing, 
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Vision Chip Architecture for Detecting Line of Sight Including Saccade
Junichi AKITA Hiroaki TAKAGI Takeshi NAGASAKI Masashi TODA Toshio KAWASHIMA Akio KITAGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1605-1611
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
vision chip, line of sight, saccade, pixel parallel processing, automata, 
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Rough Information Processing--A Computing Paradigm for Analog Systems--
Junichi AKITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1777-1779
Type of Manuscript:  Special Section LETTER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
VLSI, analog circuit, information processing, vision chip, 
 Summary | Full Text:PDF
An Image Scanning Method with Selective Activation of Tree Structure
Junichi AKITA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 956-961
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multi Processors
Keyword: 
image scan, tree structure, selective activation, automaton, image encoding, 
 Summary | Full Text:PDF
A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
Kunihiro ASADA Junichi AKITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4  pp. 436-440
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: DA/Architecture
Keyword: 
charge and discharge power, probability parameter, finite state machine, signal assignment, output probability, 
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