Jung-Lin YANG

Asynchronous Circuit Design on Field Programmable Gate Array Devices
Jung-Lin YANG Shin-Nung LU Pei-Hsuan YU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 516-522
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous, bundled-data, burst-mode, extended burst-mode, FPGA, generalized C-element, HDL, self-timed, 
 Summary | Full Text:PDF(921KB)
HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits
Jung-Lin YANG Jau-Cheng WEI Shin-Nung LU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2590-2599
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
asynchronous, burst-mode, extended burst-mode, HDL, handshake package, VHDL, Verilog, self-timed, 
 Summary | Full Text:PDF(1.6MB)
Ultra Low Power Delay Element with Post-Chip Adjustable Ability
Jung-Lin YANG Chih-Wei CHAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3381-3389
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
asynchronous circuits, bundled-data, delay-element, self-timed, low power, 
 Summary | Full Text:PDF(934KB)