Jung Hoon LEE

Implementation of Smart Dressing Systems Based on Flexible pH Sensors Using PET Films
Seok-Oh YUN Jung Hoon LEE Jin LEE Choul-Young KIM 
Publication:   
Publication Date: 2019/08/01
Vol. E102-D  No. 8  pp. 1572-1575
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
pH sensor, pH meter, smart dressing, wound infection, 
 Summary | Full Text:PDF
A Flexible Wireless Sensor Patch for Real-Time Monitoring of Heart Rate and Body Temperature
Seok-Oh YUN Jung Hoon LEE Jin LEE Choul-Young KIM 
Publication:   
Publication Date: 2019/05/01
Vol. E102-D  No. 5  pp. 1115-1118
Type of Manuscript:  LETTER
Category: Biological Engineering
Keyword: 
flexible patch, wireless sensor patch, real-time monitoring, heart rate, body temperature, 
 Summary | Full Text:PDF
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Seongjae CHO Jung Hoon LEE Yoon KIM Jang-Gn YUN Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5  pp. 596-601
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Flash/Advanced Memory
Keyword: 
NAND, flash memory, program inhibition, self-boosting, FinFET, device simulation, 
 Summary | Full Text:PDF
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
Seongjae CHO Jung Hoon LEE Gil Sung LEE Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 620-626
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
3-D nonvolatile memory, NAND flash memory array, saturation current, channel potential barrier, gate-induced barrier lowering (GIBL), 
 Summary | Full Text:PDF
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Seongjae CHO Il Han PARK Jung Hoon LEE Jang-Gn YUN Doo-Hyun KIM Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 731-735
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
memory array, electrical interference, 3-D memory device, read operation, PCI (paired cell interference), 
 Summary | Full Text:PDF
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
Jang Gn YUN Il Han PARK Seongjae CHO Jung Hoon LEE Doo-Hyun KIM Gil Sung LEE Yoon KIM Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 742-746
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
2-bit recessed channel memory, lifted-charge trapping node (L-CTN) scheme, short channel effect (SCE), second bit effect (SBE), bottom-side effect (BSE), VTH window, 
 Summary | Full Text:PDF
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices
Seongjae CHO Jang-Gn YUN Il Han PARK Jung Hoon LEE Jong Pil KIM Jong-Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 988-993
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Novel MOSFET Structures
Keyword: 
3-D devices, vertical ion implantation, doping profile, concentration peak, doping gradient, 
 Summary | Full Text:PDF