Jun YAO


Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators
Yoshikazu INAGAKI Shinya TAKAMAEDA-YAMAZAKI Jun YAO Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12  pp. 2141-2149
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
CGRAcoarse grained reconfigurable architectureacceleratorlibrarystenciloptimization
 Summary | Full Text:PDF(1.6MB)

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction
Jun YAO Yasuhiko NAKASHIMA Naveen DEVISETTI Kazuhiro YOSHIMURA Takashi NAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12  pp. 3092-3100
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
reconfigurable architecturesmulti-core processingenergy efficiency
 Summary | Full Text:PDF(1.2MB)

Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults
Yukihiro SASAGAWA Jun YAO Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12  pp. 3083-3091
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
adaptive redundancysetup error recoveryDVSlow powerAVFILP
 Summary | Full Text:PDF(2.4MB)

Selective Check of Data-Path for Effective Fault Tolerance
Tanvir AHMED Jun YAO Yuko HARA-AZUMI Shigeru YAMASHITA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8  pp. 1592-1601
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
low powerfault-tolerant computingFU array
 Summary | Full Text:PDF(903.6KB)

RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path
Yukihiro SASAGAWA Jun YAO Takashi NAKADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12  pp. 2319-2329
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
adaptive redundancysetup error recoveryDVSlow powerAVF
 Summary | Full Text:PDF(4.1MB)

An Instruction Mapping Scheme for FU Array Accelerator
Kazuhiro YOSHIMURA Takuya IWAKAMI Takashi NAKADA Jun YAO Hajime SHIMADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/02/01
Vol. E94-D  No. 2  pp. 286-297
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
instruction mappingFU arraycoarse-grained reconfigurable architecture
 Summary | Full Text:PDF(3.6MB)

A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases
Jun YAO Shinobu MIWA Hajime SHIMADA Shinji TOMITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/04/01
Vol. E91-D  No. 4  pp. 1010-1022
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
energy savingdynamic optimizationpipeline stage unificationprogram phase
 Summary | Full Text:PDF(923.7KB)