Jun TERADA


FOREWORD
Jun TERADA 
Publication:   
Publication Date: 2018/04/01
Vol. E101-B  No. 4  pp. 946-946
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF

Signaling Based Discard with Flags: Per-Flow Fairness in Ring Aggregation Networks
Yu NAKAYAMA Ken-Ichi SUZUKI Jun TERADA Akihiro OTAKA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2015/12/01
Vol. E98-B  No. 12  pp. 2431-2438
Type of Manuscript:  PAPER
Category: Network
Keyword: 
metro access networksring aggregationfairnessflag
 Summary | Full Text:PDF

Error Vector Magnitude Evaluation of Terahertz Transmitter Employing Optical Frequency Comb
Shigeru KUWANO Daisuke IIDA Jun TERADA Akihiro OTAKA Naoto YOSHIMOTO Shintaro HISATAKE Tadao NAGATSUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/08/01
Vol. E98-C  No. 8  pp. 799-807
Type of Manuscript:  Special Section PAPER (Special Section on Microwave Photonics)
Category: MWP Subsystem
Keyword: 
terahertz transmissionoptical frequency comberror vector magnitude
 Summary | Full Text:PDF

An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System
Hiroaki KATSURAI Hideki KAMITSUNA Hiroshi KOIZUMI Jun TERADA Yusuke OHTOMO Tsugumichi SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4  pp. 582-588
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
clock and data recoveryoptical communicationreceiversburst mode1G/10G PON10G-EPON
 Summary | Full Text:PDF

A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks
Jun TERADA Yasuyuki MATSUYA Shin'ichiro MUTOH Yuichi KADO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 479-483
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Analog
Keyword: 
A/D convertersample holdFD-SOIlow voltage
 Summary | Full Text:PDF

8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region
Jun TERADA Yasuyuki MATSUYA Fumiharu MORISAWA Yuichi KADO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2  pp. 313-317
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
A/D converterlow voltagelow powerbubble errormonotonicity
 Summary | Full Text:PDF