Jun SHIOMI


A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation
Kentaro NAGAI Jun SHIOMI Hidetoshi ONODERA 
Publication:   
Publication Date: 2021/10/01
Vol. E104-C  No. 10  pp. 617-624
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
body bias generatorminimum energy point tracking (MEPT)adaptive body bias (ABB)analog-assisted digital
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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing
Hongjie XU Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   
Publication Date: 2019/12/01
Vol. E102-A  No. 12  pp. 1741-1750
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
standard-cell memorySRAMnear-threshold computingcache memorysystem-on-chip
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Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits
Ryosuke MATSUO Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA Akihiko SHINYA Masaya NOTOMI 
Publication:   
Publication Date: 2019/12/01
Vol. E102-A  No. 12  pp. 1751-1759
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagramlogic circuitoptical circuit
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A Design Method of a Cell-Based Amplifier for Body Bias Generation
Takuya KOYANAGI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   
Publication Date: 2019/07/01
Vol. E102-C  No. 7  pp. 565-572
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
body bias generatorcell-based-designanalog-assisted digitalamplifierlow power
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A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation
Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12  pp. 2764-2775
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
minimum energy point tracking (MEPT)dynamic voltage and frequency scaling (DVFS)adaptive body biasing (ABB)standard-cell based memory (SCM)
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Analytical Stability Modeling for CMOS Latches in Low Voltage Operation
Tatsuya KAMAKARI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2463-2472
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
latchlow voltage designstability modeling
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Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization
Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1455-1466
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
near-threshold computingstatistical static timing analysis (SSTA)
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