IEICE Trans

Jun SHIOMI

Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation Naoki HATTORI Jun SHIOMI Yutaka MASUDA Tohru ISHIHARA Akihiko SHINYA Masaya NOTOMI
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1477-1487 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: neural network, optical circuit, multi-layer perceptron, wavelength division multiplexing,
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A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits Ryosuke MATSUO Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA Akihiko SHINYA Masaya NOTOMI
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1546-1554 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: binary decision diagram, logic circuit, optical circuit,
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Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration Hongjie XU Jun SHIOMI Hidetoshi ONODERA
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1488-1498 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: convolutional neural networks, machine learning, low power circuit design, VLSI, parallel processing,
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Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region Shoya SONODA Jun SHIOMI Hidetoshi ONODERA
Publication: Publication Date: 2021/11/01 Vol. E104-A No. 11 pp. 1566-1576 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB),
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A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation Kentaro NAGAI Jun SHIOMI Hidetoshi ONODERA
Publication: Publication Date: 2021/10/01 Vol. E104-C No. 10 pp. 617-624 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: body bias generator, minimum energy point tracking (MEPT), adaptive body bias (ABB), analog-assisted digital,
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Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits Ryosuke MATSUO Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA Akihiko SHINYA Masaya NOTOMI
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 pp. 1751-1759 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: binary decision diagram, logic circuit, optical circuit,
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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing Hongjie XU Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 pp. 1741-1750 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: standard-cell memory, SRAM, near-threshold computing, cache memory, system-on-chip,
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A Design Method of a Cell-Based Amplifier for Body Bias Generation Takuya KOYANAGI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 pp. 565-572 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: body bias generator, cell-based-design, analog-assisted digital, amplifier, low power,
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A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 pp. 2764-2775 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: minimum energy point tracking (MEPT), dynamic voltage and frequency scaling (DVFS), adaptive body biasing (ABB), standard-cell based memory (SCM),
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Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Tatsuya KAMAKARI Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 pp. 2463-2472 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: latch, low voltage design, stability modeling,
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Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization Jun SHIOMI Tohru ISHIHARA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1455-1466 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: near-threshold computing, statistical static timing analysis (SSTA),
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