Jun Gyu LEE

Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers
Jun Gyu LEE Zule XU Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8  pp. 1337-1346
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
phase-locked loopfrequency synthesizerloop designsettling timeprocess variations
 Summary | Full Text:PDF(1.9MB)

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL
Zule XU Jun Gyu LEE Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 1065-1068
Type of Manuscript:  BRIEF PAPER
digital delta-sigma modulator (DDSM)fractional-N PLLdither
 Summary | Full Text:PDF(574.2KB)

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology
Takayuki KONISHI Kenji INAZU Jun Gyu LEE Masanori NATSUI Shoichi MASUI Boris MURMANN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3  pp. 334-345
Type of Manuscript:  PAPER
Category: Electronic Circuits
operational transconductance amplifierdesign optimizationanalog design methodologylow power design
 Summary | Full Text:PDF(1.4MB)