Jun DEGUCHI

A Noise-Canceling Charge Pump for Area Efficient PLL Design
Go URAKAWA Hiroyuki KOBAYASHI Jun DEGUCHI Ryuichi FUJIMOTO 
Publication:   
Publication Date: 2021/10/01
Vol. E104-C  No. 10  pp. 625-634
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
PLL, frequency synthesizer, phase-locked loop, charge pump, noise-cancel, phase noise, jitter, in-band noise, occupied area, 
 Summary | Full Text:PDF
Weight Compression MAC Accelerator for Effective Inference of Deep Learning
Asuka MAKI Daisuke MIYASHITA Shinichi SASAKI Kengo NAKATA Fumihiko TACHIBANA Tomoya SUZUKI Jun DEGUCHI Ryuichi FUJIMOTO 
Publication:   
Publication Date: 2020/10/01
Vol. E103-C  No. 10  pp. 514-523
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: Integrated Electronics
Keyword: 
deep learning, convolutional neural network, quantization, variable bit width, post-training, inference, accelerator, processor, FPGA, 
 Summary | Full Text:PDF
A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter
Daisuke MIYASHITA Hiroyuki KOBAYASHI Jun DEGUCHI Shouhei KOUSAI Mototsugu HAMADA Ryuichi FUJIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/06/01
Vol. E95-C  No. 6  pp. 1008-1016
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
ADPLL, TDC, phase interpolator, phase noise, 
 Summary | Full Text:PDF