IEICE Trans

Juinn-Dar HUANG

TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance Ya-Shih HUANG Han-Yuan CHANG Juinn-Dar HUANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/08/01 Vol. E98-A No. 8 pp. 1796-1805 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: thermal-aware placement and routing, design for quality, field programmable gate arrays (FPGAs), 3D ICs, 3D FPGAs,
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ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication Bu-Ching LIN Juinn-Dar HUANG Jing-Yang JOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/04/01 Vol. E97-A No. 4 pp. 931-939 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: finite impulse response (FIR) filter, multiple constant multiplication (MCM), bitwidth, integer linear programming (ILP),
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Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay Juinn-Dar HUANG Chia-I CHEN Wan-Ling HSU Yen-Ting LIN Jing-Yang JOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/02/01 Vol. E95-A No. 2 pp. 559-566 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: Behavioral synthesis, distributed register-file, performance optimization, low-power, resource binding, scheduling,
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Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture Juinn-Dar HUANG Chia-I CHEN Yen-Ting LIN Wan-Ling HSU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/04/01 Vol. E94-A No. 4 pp. 1151-1155 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: communication synthesis, distributed register-file microarchitecture, interconnect minimization, resource binding, scheduling,
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A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication Chia-I CHEN Juinn-Dar HUANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 pp. 1300-1308 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: multicycle communication, architectural synthesis, high-level synthesis, performance-driven, criticality-driven,
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Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture Ya-Shih HUANG Yu-Ju HONG Juinn-Dar HUANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3143-3150 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: multicycle communication, communication synthesis, interconnect minimization, resource allocation, resource sharing, scheduling, routing,
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A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping Jie-Hong JIANG Jing-Yang JOU Juinn-Dar HUANG Jung-Shian WEI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 pp. 1813-1819 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: binary decision diagrams, equivalent class, Roth-Karp decomposition, LUT-based FPGA,
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