Jui-Hung HUNG


Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering
Wei-Kai CHENG Jui-Hung HUNG Yi-Hsuan CHIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12  pp. 2388-2397
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
clock network synthesisclock meshclock gating
 Summary | Full Text:PDF

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits
Hsin-Hsiung HUANG Jui-Hung HUNG Cheng-Chiang LIN Tsai-Ming HSIEH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11  pp. 2402-2411
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
analog circuitswire planning with obstacleselectromigrationinterferenceinteger linear programming
 Summary | Full Text:PDF