Juho KIM


Efficient False Aggressors Pruning with Functional Correlation
Hyungwoo LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3159-3165
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
signal integrityfalse aggressorcrosstalktiming analysis
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Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
Sungjae KIM Hyungwoo LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A  No. 1  pp. 234-240
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low powerglitchgate sizingbuffer insertion
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A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing
Sungkun LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/10/01
Vol. E84-A  No. 10  pp. 2553-2560
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
buffer insertiontransistor sizingoptimization
 Summary | Full Text:PDF