Juebang YU


Memristor Model for SPICE
Xuliang ZHANG Zhangcai HUANG Juebang YU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 355-360
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
memristorSPICE modelChua's circuitmemristor device and circuit simulation
 Summary | Full Text:PDF

VLSI Floorplanning with Boundary Constraints Based on Single-Sequence Representation
Kang LI Juebang YU Jian LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9  pp. 2369-2375
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI physical designfloorplan/placementboundary constraintssingle-sequence
 Summary | Full Text:PDF

An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation
Jing LI Juebang YU Hiroshi MIYASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12  pp. 3398-3404
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan and Placement
Keyword: 
O-tree representationincremental placementBBLVLSI circuit physical design
 Summary | Full Text:PDF