Ju Hee CHOI

RRWL: Round Robin-Based Wear Leveling Using Block Erase Table for Flash Memory
Seon Hwan KIM Ju Hee CHOI Jong Wook KWAK 
Publication:   
Publication Date: 2017/05/01
Vol. E100-D  No. 5  pp. 1124-1127
Type of Manuscript:  LETTER
Category: Software System
Keyword: 
flash memory, wear leveling, hidden cold block problem, bit array table, block erase table, 
 Summary | Full Text:PDF
Migration Cost Sensitive Garbage Collection Technique for Non-Volatile Memory Systems
Sang-Ho HWANG Ju Hee CHOI Jong Wook KWAK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12  pp. 3177-3180
Type of Manuscript:  LETTER
Category: Software System
Keyword: 
non-volatile memory, garbage collection, wear leveling, migration cost, update frequency, 
 Summary | Full Text:PDF
PBGC: Proxy Block-Based Garbage Collection for Index Structures in NAND Flash Memory
Seon Hwan KIM Ju Hee CHOI Jong Wook KWAK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/07/01
Vol. E99-D  No. 7  pp. 1928-1932
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
garbage collection, NAND flash memory, index structure, proxy block, 
 Summary | Full Text:PDF
HaWL: Hidden Cold Block-Aware Wear Leveling Using Bit-Set Threshold for NAND Flash Memory
Seon Hwan KIM Ju Hee CHOI Jong Wook KWAK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4  pp. 1242-1245
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
wear leveling, NAND flash memory, bit array table, hidden cold block problem, bit-set threshold, 
 Summary | Full Text:PDF
Write Avoidance Cache Coherence Protocol for Non-volatile Memory as Last-Level Cache in Chip-Multiprocessor
Ju Hee CHOI Jong Wook KWAK Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/08/01
Vol. E97-D  No. 8  pp. 2166-2169
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
cache coherence, non volatile memory, STT-RAM, chip multi-processor, 
 Summary | Full Text:PDF
Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor
Ju Hee CHOI Jong Wook KWAK Seong Tae JHANG Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/04/01
Vol. E97-D  No. 4  pp. 972-975
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
filter cache, L0 cache, data cache, partial tag, partial address, 
 Summary | Full Text:PDF