Jong Duk LEE


Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
Sang Hyuk PARK Sangwoo KANG Seongjae CHO Dong-Seup LEE Jung Han LEE Hong-Seon YANG Kwon-Chil KANG Joung-Eob LEE Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 647-652
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
single electron transistorrecessed channelMOSFET current suppression
 Summary | Full Text:PDF

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
Seongjae CHO Jung Hoon LEE Gil Sung LEE Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 620-626
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
3-D nonvolatile memoryNAND flash memory arraysaturation currentchannel potential barriergate-induced barrier lowering (GIBL)
 Summary | Full Text:PDF

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
Jongwook JEON Ickhyun SONG Jong Duk LEE Byung-Gook PARK Hyungcheol SHIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 627-634
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
CMOSchannel thermal noiseradio frequency integrated circuit (RFIC)low noise amplifier (LNA)noise figure
 Summary | Full Text:PDF

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
Doo-Hyun KIM Il Han PARK Seongjae CHO Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 659-663
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
SONOSflash memorynitride-based charge trap memoryretentionmulti-bitdouble gate
 Summary | Full Text:PDF

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
Yoon KIM Seongjae CHO Gil Sung LEE Il Han PARK Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 653-658
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
NANDflash memorystacked NANDvertical channel
 Summary | Full Text:PDF

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Seongjae CHO Il Han PARK Jung Hoon LEE Jang-Gn YUN Doo-Hyun KIM Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 731-735
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
memory arrayelectrical interference3-D memory deviceread operationPCI (paired cell interference)
 Summary | Full Text:PDF

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
Jang Gn YUN Il Han PARK Seongjae CHO Jung Hoon LEE Doo-Hyun KIM Gil Sung LEE Yoon KIM Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5  pp. 742-746
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
2-bit recessed channel memorylifted-charge trapping node (L-CTN) schemeshort channel effect (SCE)second bit effect (SBE)bottom-side effect (BSE)VTH window
 Summary | Full Text:PDF

Design and Simulation of Asymmetric MOSFETs
Jong Pil KIM Woo Young CHOI Jae Young SONG Seongjae CHO Sang Wan KIM Jong Duk LEE Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5  pp. 978-982
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Junction Formation and TFT Reliability
Keyword: 
asymmetric MOSFETLDDmesa structuresidewall spacer gate
 Summary | Full Text:PDF