IEICE Trans

Jon T. BUTLER

A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 pp. 1583-1591 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: index generation functions, linear decomposition, incompletely specified functions, balanced decision tree, content-addressable memory, logic design, heuristic,
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On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER Mitchell A. THORNTON Theodore W. MANIKAS
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/09/01 Vol. E97-D No. 9 pp. 2234-2242 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: minimization algorithm of the number of edges, EVMDDs, grouping variables for optimization of decision diagrams, multi-state systems, system analysis using decision diagrams,
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A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2059-2067 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: two-variable numeric function generators (NFGs), edge-valued multiple-valued decision diagrams (EVMDDs), edge-valued binary decision diagrams (EVBDDs), graph-based representation of numeric functions, programmable memory-based architecture,
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A Quaternary Decision Diagram Machine: Optimization of Its Code Tsutomu SASAO Hiroki NAKAHARA Munehiro MATSUURA Yoshifumi KAWAMURA Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2026-2035 Type of Manuscript: INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Keyword: quarternary decision diagram, branching program machine,
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Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2752-2761 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis and Verification Keyword: edge-valued binary decision diagrams (EVBDDs), recursive segmentation, piecewise polynomial approximation, numerical function generators (NFGs), programmable architecture,
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Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3510-3518 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: LUT cascades, 2nd-order Chebyshev approximation, non-uniform segmentation, NFGs, automatic synthesis, FPGA,
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Bi-Partition of Shared Binary Decision Diagrams Munehiro MATSUURA Tsutomu SASAO Jon T. BUTLER Yukihiro IGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2693-2700 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: shared binary decision diagram, SBDD, bi-partition, multiple-output function, decomposition,
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