Jiun-In GUO

A Verification-Aware Design Methodology for Thread Pipelining Parallelization
Guo-An JIAN Cheng-An CHIEN Peng-Sheng CHEN Jiun-In GUO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/10/01
Vol. E95-D  No. 10  pp. 2505-2513
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
verification3D depth map generationpipelineparallel computingbehavior model
 Summary | Full Text:PDF(1.7MB)

The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning
Hun-Chen CHEN Tian-Sheuan CHANG Jiun-In GUO Chein-Wei JEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5  pp. 1061-1069
Type of Manuscript:  PAPER
Category: Electronic Circuits
discrete Hartley transformdistributed arithmeticcyclic preserving partitioningcomputation sharing
 Summary | Full Text:PDF(2.2MB)