Jiro IDA


Analysis of Super-Steep Subthreshold Slope Body-Tied SOI MOSFET and its Possibility for Ultralow Voltage Application
Takayuki MORI Jiro IDA 
Publication:   
Publication Date: 2018/11/01
Vol. E101-C  No. 11  pp. 916-922
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
body-tiedfloating-bodySOIsteep subthreshold slopeultralow power
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Characterization of Hysteresis in SOI-Based Super-Steep Subthreshold Slope FETs
Takayuki MORI Jiro IDA Shota INOUE Takahiro YOSHIDA 
Publication:   
Publication Date: 2018/05/01
Vol. E101-C  No. 5  pp. 334-337
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
SOIsteep subthreshold slopefloating body effectfeedbackhysteresis
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Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme
Koichi MORIKAWA Jiro IDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12  pp. 1713-1719
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
local wiringjunction capacitanceembedded SRAMcoupling noise
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A Highly Drivable CMOS Design with Very Narrow Sidewall and Novel Channel Profile for 3.3 V High Speed Logic Application
Jiro IDA Satoshi ISHII Youko KAJITA Tomonobu YOKOYAMA Masayoshi INO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4  pp. 525-531
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
CMOSLDDhot-carrier-reliabilitymultiplier
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