IEICE Trans

Jinian BIAN

Pruning-Based Trace Signal Selection Algorithm for Data Acquisition in Post-Silicon Validation Kang ZHAO Jinian BIAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/06/01 Vol. E95-A No. 6 pp. 1030-1040 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: algorithm, silicon debug, state restoration, trace signal selection,
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Processor Accelerator Customization through Data Flow Graph Exploration Kang ZHAO Jinian BIAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/07/01 Vol. E94-A No. 7 pp. 1540-1552 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: algorithm, instruction-set extension (ISE), graph exploration,
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Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory Yanni ZHAO Jinian BIAN Shujun DENG Zhiqiu KONG Kang ZHAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3086-3093 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: constrained random simulation, stimulus generation, SAT, piecewise-uniform, tabu search with memory,
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Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation Junbo YU Qiang ZHOU Gang QU Jinian BIAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3151-3159 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: peak temperature, rebinding, reallocation, behavioral synthesis,
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Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 pp. 2283-2294 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: application partitioning, CAD algorithm, MPSoC, ASIP, synthesis,
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Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 pp. 2456-2464 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Electronic Circuits and Systems Keyword: hardware/software partitioning, CAD algorithm, search space smoothing, MPSoC, ASIP,
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Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/06/01 Vol. E91-A No. 6 pp. 1478-1487 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: custom instruction identification, basic convex pattern (BCP), system-on-a-chip (SoC), application specific instruction-set processor (ASIP),
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Accelerating Logic Rewiring Using Implication Analysis Tree Chin-Ngai SZE Wangning LONG Yu-Liang WU Jinian BIAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2725-2736 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: alternative wire, logic transformation, logic synthesis,
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