Jing-ling YANG


Parallel Test Structure in Latch Based Asynchronous Pipeline
Jing-ling YANG Chiu-sing CHOY Cheong-Fat CHAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2527-2529
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
asynchronouspipelineevent logiclatchtest
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