IEICE Trans

Jing-Yang JOU

Power-Efficient Instancy Aware DRAM Scheduling Gung-Yu PAN Chih-Yen LAI Jing-Yang JOU Bo-Cheng Charles LAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/04/01 Vol. E98-A No. 4 pp. 942-953 Type of Manuscript: PAPER Category: Systems and Control Keyword: DRAM, dynamic power management, energy-aware systems, scheduling,
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ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication Bu-Ching LIN Juinn-Dar HUANG Jing-Yang JOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/04/01 Vol. E97-A No. 4 pp. 931-939 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: finite impulse response (FIR) filter, multiple constant multiplication (MCM), bitwidth, integer linear programming (ILP),
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Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay Juinn-Dar HUANG Chia-I CHEN Wan-Ling HSU Yen-Ting LIN Jing-Yang JOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/02/01 Vol. E95-A No. 2 pp. 559-566 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: Behavioral synthesis, distributed register-file, performance optimization, low-power, resource binding, scheduling,
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Efficient Vector Compaction Methods for Power Estimation with Consecutive Sampling Techniques Chih-Yang HSU Chien-Nan Jimmy LIU Jing-Yang JOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/11/01 Vol. E87-A No. 11 pp. 2973-2982 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: power estimation, vector compaction, grouping, consecutive sampling, random sampling,
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An Efficient Power Model for IP-Level Complex Designs Chih-Yang HSU Chien-Nan Jimmy LIU Jing-Yang JOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/08/01 Vol. E86-A No. 8 pp. 2073-2080 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: IP-level, power model, lookup table, dynamic grouping,
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Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs Hsien-Ho CHUANG Jing-Yang JOU C. Bernard SHUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2545-2551 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Performance Optimization Keyword: technology mapping, FPGA, hard-wired, non-homogeneous, XC4000,
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A New Method for Constructing IP Level Power Model Based on Power Sensitivity Heng-Liang HUANG Jiing-Yuan LIN Wen-Zen SHEN Jing-Yang JOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2431-2438 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Methodology Keyword: IP, power model, power sensitivity,
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Internet-Based Hierarchical Floorplan Design Jiann-Horng LIN Jing-Yang JOU Iris Hui-Ru JIANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/25 Vol. E82-A No. 11 pp. 2414-2423 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: internet, floorplanning,
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A Variable Partitioning Algorithm of BDD for FPGA Technology Mapping Jie-Hong JIANG Jing-Yang JOU Juinn-Dar HUANG Jung-Shian WEI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 pp. 1813-1819 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: binary decision diagrams, equivalent class, Roth-Karp decomposition, LUT-based FPGA,
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