Jin CHEN


An Algorithm for Estimating Bottleneck Effect in Series-Parallel Tree Circuits
Molin CHANG Wang-Jin CHEN Jyh-Herng WANG Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/11/25
Vol. E81-A  No. 11  pp. 2400-2406
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
waveform-based switch-level timing simulatorslope estimationbottleneck effect
 Summary | Full Text:PDF(620.8KB)

Pattern-Based Maximal Power Estimation for VLSI Chip Design
Wang-Jin CHEN Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/11/25
Vol. E80-A  No. 11  pp. 2300-2307
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
maximal power dissipationsimulated annealingwalk throughpower estimationpower optimization
 Summary | Full Text:PDF(653.4KB)