Jen-Chieh LIU

A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration
Ting-Chou LU Ming-Dou KER Hsiao-Wen ZAN Jen-Chieh LIU Yu LEE 
Publication Date: 2017/01/01
Vol. E100-A  No. 1  pp. 275-282
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
crystal-less clock generatormulti-phase outputdigital power applicationprocessvoltage and temperature (PVT) calibration
 Summary | Full Text:PDF(2.8MB)

A Low Power Pulse Generator for Test Platform Applications
Jen-Chieh LIU Pei-Ying LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1415-1416
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
arbitrary waveformpulse generatorlow power
 Summary | Full Text:PDF(569KB)

Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture
Yo-Hao TU Jen-Chieh LIU Kuo-Hsing CHENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 655-658
Type of Manuscript:  BRIEF PAPER
static-phase-errordelay-locked-loopfrequency multiplieredge-combinertime amplifier
 Summary | Full Text:PDF(1MB)