Ittetsu TANIGUCHI


ILP-Based Scheduling for Parallelizable Tasks
Kana SHIMADA Shogo KITANO Ittetsu TANIGUCHI Hiroyuki TOMIYAMA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1503-1505
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
task scheduling; integer linear programming
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Static Mapping of Parallelizable Tasks under Deadline Constraints
Yining XU Ittetsu TANIGUCHI Hiroyuki TOMIYAMA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1500-1502
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
task mappingmanycore embedded systemsinteger linear programming
 Summary | Full Text:PDF

A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers
Takahiro YAMAMOTO Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Shigeru YAMASHITA Yuko HARA-AZUMI 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1496-1499
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
approximate computingarray multipliersSMT solver
 Summary | Full Text:PDF

Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems
Yining XU Yang LIU Junya KAIDA Ittetsu TANIGUCHI Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7  pp. 1417-1419
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
application mappingmanycore embedded systemsinteger linear programming
 Summary | Full Text:PDF

Autonomous Decentralized Mechanism for Energy Interchanges with Accelerated Diffusion Based on MCMC
Yusuke SAKUMOTO Ittetsu TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1504-1511
Type of Manuscript:  PAPER
Category: Systems and Control
Keyword: 
renewable energymicrogridautonomous decentralized controlpower routing
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Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs
Ittetsu TANIGUCHI Junya KAIDA Takuji HIEDA Yuko HARA-AZUMI Hiroyuki TOMIYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/11/01
Vol. E97-D  No. 11  pp. 2827-2834
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
many-core SoCsapplication mappingsystem-level designembedded systems
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Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path
Ittetsu TANIGUCHI Kohei AOKI Hiroyuki TOMIYAMA Praveen RAGHAVAN Francky CATTHOOR Masahiro FUKUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2  pp. 606-615
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
design space explorationarchitecture explorationvery long instruction-set word (VLIW) processorgenetic algorithm (GA)
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Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs
Junya KAIDA Yuko HARA-AZUMI Takuji HIEDA Ittetsu TANIGUCHI Hiroyuki TOMIYAMA Koji INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/10/01
Vol. E96-D  No. 10  pp. 2268-2271
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
many-core SoCsapplication mappingsystem-level designembedded systems
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Network Topology and Battery Size Exploration for Decentralized Energy Network with MIP Base Power Flow Optimization
Ittetsu TANIGUCHI Kazutoshi SAKAKIBARA Shinya KATO Masahiro FUKUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7  pp. 1617-1624
Type of Manuscript:  PAPER
Category: General Fundamentals and Boundaries
Keyword: 
design optimizationmixed integer programming (MIP)combinatorial optimization problemsmart grid
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Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
Ittetsu TANIGUCHI Ayataka KOBAYASHI Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2659-2668
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
forward error correction (FEC)decoder model
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Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
Ittetsu TANIGUCHI Praveen RAGHAVAN Murali JAYAPALA Francky CATTHOOR Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 1161-1173
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
address generation unit (AGU)reconfigurable architectureASIP designarchitecture exploration
 Summary | Full Text:PDF