Itsuo TAKANAMI


Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant
Tadayoshi HORITA Itsuo TAKANAMI Masatoshi MORI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/04/01
Vol. E91-D  No. 4  pp. 1168-1175
Type of Manuscript:  PAPER
Category: Biocybernetics, Neurocomputing
Keyword: 
multilayer neural networkfault-toleranceweight faultneuron faultmultiple fault
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An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
Tadayoshi HORITA Yuuji KATOU Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2  pp. 623-632
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
3D mesh-connected processor arrays1.5-track switchesreconfigurationfault toleranceredundancy
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Self-Reconfiguring of -Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit
Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/10/01
Vol. E87-D  No. 10  pp. 2318-2328
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
mesh arrayfault-tolerancereconfigurationself-repairbuilt-in circuit
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An Efficiently Self-Reconstructing Array System Using E-1-Track Switches
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2743-2752
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
mesh-connected processor arrays1-track switchesE-1-track switchesfault-tolerancereconfigurable architecture
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A Novel Learning Algorithm Which Makes Multilayer Neural Networks Multiple-Weight-Fault Tolerant
Itsuo TAKANAMI Yasuhiro OYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2536-2543
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Dependable Systems
Keyword: 
multilayer neural networkfault tolerancemultiple weight faultfault injectionlearning algorithm
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A System for Efficiently Self-Reconstructing 1(1/2)-Track Switch Torus Arrays
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/12/01
Vol. E84-D  No. 12  pp. 1801-1809
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
reconfiguration1(1/2)-track switch torus arrayfault tolerancewafer scale integrationself-reconfigurable system
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A Graph-Theoretic Approach to Minimizing the Number of Dangerous Processors in Fault-Tolerant Mesh-Connected Processor Arrays
Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Vol. E84-D  No. 11  pp. 1462-1470
Type of Manuscript:  Special Section PAPER (Special Issue on Function Integrated Information Systems)
Category: 
Keyword: 
fault tolerancereconfiguration algorithmdangerous processormesh-connected processor arraygraph-theoretic approach
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An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/08/25
Vol. E83-D  No. 8  pp. 1701-1705
Type of Manuscript:  LETTER
Category: Fault Tolerance
Keyword: 
fault tolerant processor arrays1 1/2 track-switch modelself-reconfigurable systemrun-time fault tolerancewafer scale integration
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A Built-in Self-Reconfigurable Scheme for 3D Mesh Arrays
Itsuo TAKANAMI Tadayoshi HORITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12  pp. 1554-1562
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault tolerancereconstructionthree-dimensional mesh arrayself-reconstructionhardware algorithm
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An Efficient Method for Reconfiguring the 1 1/2 Track-Switch Mesh Array
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12  pp. 1545-1553
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
mesh-connected parallel computerwafer scale integrationyield enhancementfault tolerance1 1/2 track-switch model
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Self-Reconstruction of 3D Mesh Arrays with 1 1/2-Track Switches by Digital Neural Circuits
Itsuo TAKANAMI Satoru NAKAMURA Tadayoshi HORITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9  pp. 1678-1686
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Configurable Computing and Fault Tolerance
Keyword: 
fault tolerancethree-dimensional mesh arrayself-reconstructionneural algorithmneural circuit
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An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/25
Vol. E80-D  No. 9  pp. 879-885
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Fault Tolerance
Keyword: 
mesh-arraydefect tolerancelink faultPE faultwafer scale integration
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A Built-In Self-Reconstruction Approach for Partitioned Mesh-Arrays Using Neural Algorithm
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8  pp. 1160-1167
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Fault Diagnosis/Tolerance
Keyword: 
mesh-arrayfault toleranceself-reconfigurable systemwafer scale integrationneural algorithm
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Three-Dimensionally Fully Space Constructible Functions
Makoto SAKAMOTO Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/06/25
Vol. E77-D  No. 6  pp. 723-725
Type of Manuscript:  LETTER
Category: Artificial Intelligence and Cognitive Science
Keyword: 
multihead Turing machinethree-dimensional Turing machinespace complexityfully space constructible function
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Multihead Finite Automata with Markers
Yue WANG Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4  pp. 615-620
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
multihead finite automatonmarker finite automatahierarchyone-letter alphabet
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Hierarchical Properties of Realtime One-Way Alternating Multi-Stack-Counter Automata
Tsunehiro YOSHINAGA Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4  pp. 621-629
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
alternating automataone-way counterone-way stack-countercomputational complexity
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Leaf-Size Bounded Real-Time Synchronized Alternating One-Way Multicounter Machines
Hiroshi MATSUNO Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/03/25
Vol. E77-D  No. 3  pp. 351-354
Type of Manuscript:  LETTER
Category: Automaton, Language and Theory of Computing
Keyword: 
alternationsynchronized alternationmulticounter machine and real-time computation
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A Note on One-Way Multicounter Machines and Cooperating Systems of One-Way Finite Automata
Yue WANG Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/10/25
Vol. E76-D  No. 10  pp. 1302-1306
Type of Manuscript:  LETTER
Category: Automaton, Language and Theory of Computing
Keyword: 
one-way multicounter automatacooperating systems of one-way finite automatahierarchycomputational complexity
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Some Hierarchy Results on Multihead Automata over a One-Letter Alphabet
Yue WANG Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/06/25
Vol. E76-D  No. 6  pp. 625-633
Type of Manuscript:  PAPER
Category: Automaton, Language and Theory of Computing
Keyword: 
sensing multihead automataautomata on two-dimensional tapesone-letter alphabethierarchycomputational complexity
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A Two-Way Nondeterministic One-Counter Languages Not Accepted by Nondeterministic Rebound Automata
Makoto SAKAMOTO Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1990/06/25
Vol. E73-E  No. 6  pp. 879-881
Type of Manuscript:  LETTER
Category: Automaton, Language and Theory of Computing
Keyword: 
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A Note on Synchronized Alternating Turing Machines with Small Space Bounds
Katsushi INOUE Itsuo TAKANAMI Akira ITO Hiroshi MATSUNO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/11/25
Vol. E72-E  No. 11  pp. 1182-1184
Type of Manuscript:  LETTER
Category: Automation, Language and Theory of Computing
Keyword: 
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Some Closure Properties of the Class of Sets Accepted by Three-Way Two-Dimensional Alternating Finite Automata
Akira ITO Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/04/25
Vol. E72-E  No. 4  pp. 348-350
Type of Manuscript:  LETTER
Category: Automation, Language and Theory of Computing
Keyword: 
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Some Realizations of Multi-Valued Logic Functions with Cellular Arrays
Itsuo TAKANAMI Katsushi INOUE 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/03/25
Vol. E72-E  No. 3  pp. 235-240
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
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Alternating Multihead Finite Automata with Constant Leaf-Sizes
Hiroshi MATSUNO Katsushi INOUE Itsuo TAKANAMI Hiroshi TANIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1988/10/25
Vol. E71-E  No. 10  pp. 1006-1012
Type of Manuscript:  PAPER
Category: Automaton, Language and Theory of Computing
Keyword: 
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A Note on Alternating Turing Machines Using Small Space
Akira ITO Katsushi INOUE Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/10/25
Vol. E70-E  No. 10  pp. 990-996
Type of Manuscript:  PAPER
Category: Automaton, Language and Theory of Computing
Keyword: 
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A Note on Reversal Complexities of Real-Time Counter Machines
Hiroshi MATSUNO Katsushi INOUE Itsuo TAKANAMI Hiroshi TANIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/08/25
Vol. E69-E  No. 8  pp. 838-839
Type of Manuscript:  LETTER
Category: Automata and Languages
Keyword: 
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Alternating One-Way Multihead Turing Machines with Only Universal States
Shunichi SAKURAYAMA Hiroshi MATSUNO Katsushi INOUE Itsuo TAKANAMI Hiroshi TANIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1985/10/25
Vol. E68-E  No. 10  pp. 705-711
Type of Manuscript:  PAPER
Category: Automata and Languages
Keyword: 
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A Decoder for DEC-TED BCH Codes
Hirokazu OKANO Itsuo TAKANAMI Kazuo MORIKAWA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1984/07/25
Vol. E67-E  No. 7  pp. 393-394
Type of Manuscript:  LETTER
Category: Data Transmission
Keyword: 
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A Note on Space Complexity of Nondeterministic Two-Dimensional Turing Machines
Akira ITO Katsushi INOUE Itsuo TAKANAMI Hiroshi TANIGUCHI 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1983/08/25
Vol. E66-E  No. 8  pp. 508-509
Type of Manuscript:  LETTER
Category: Automata and Languages
Keyword: 
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A Note on Alternating On-Line Turing Machines with Only Universal States
Katsushi INOUE Itsuo TAKANAMI Hiroshi TANIGUCHI Akira ITO 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1983/06/25
Vol. E66-E  No. 6  pp. 395-396
Type of Manuscript:  LETTER
Category: Automata and Languages
Keyword: 
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