IEICE SEARCH SYSTEM

Isao SHIRAKAWA

Area-Efficient Reconfigurable Architecture for Media Processing Yukio MITSUYAMA Kazuma TAKAHASHI Rintaro IMAI Masanori HASHIMOTO Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3651-3662 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: reconfigurable, media processing, multi-standard, area-efficiency, dynamic reconfiguration,
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Transistor Sizing of LCD Driver Circuit for Technology Migration Masanori HASHIMOTO Takahito IJICHI Shingo TAKAHASHI Shuji TSUKIYAMA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2712-2717 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: technology migration, transistor sizing, LCD driver circuit,
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A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays Shingo TAKAHASHI Shuji TSUKIYAMA Masanori HASHIMOTO Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3538-3545 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: active matrix LCD, CAD tool, column driver, sampling pulse, sampling switch,
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Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation Gen FUJITA Takaaki IMANAKA Hyunh Van NHAT Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 941-949 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: object extraction, moving picture, human object, color space,
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Design of Ogg Vorbis Decoder System for Embedded Platform Atsushi KOSAKA Hiroyuki OKUHATA Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/08/01 Vol. E88-A No. 8 pp. 2124-2130 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from the 19th Symposium on Signal Processing) Category: VLSI Design Technology and CAD Keyword: embedded system design, Ogg Vorbis decoder, MDCT, residue decoding process,
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Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems Yukio MITSUYAMA Motoki KIMURA Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 899-906 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: IEEE802.11i, WEP, TKIP, AES-CCM, embedded system, low hardware cost,
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Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays Sadahiro TANI Yoshihiro UCHIDA Makoto FURUIE Shuji TSUKIYAMA BuYeol LEE Shuji NISHI Yasushi KUBOTA Isao SHIRAKAWA Shigeki IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2923-2932 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, LCD, parasitic capacitance, signal integrity, circuit simulation,
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Implementation of Java Accelerator for High-Performance Embedded Systems Motoki KIMURA Morgan Hirosuke MIKI Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3079-3088 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation Accelerator Keyword: embedded systems, Java, Java virtual machine, instruction folding, J2ME,
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Object Sharing Scheme for Heterogeneous Environment Katsuya NAKAGAWA Masaru KAWAKITA Koji SATO Mitsuru MINAKUCHI Takao ONOYE Toru CHIBA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 813-821 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: heterogeneous environment, object sharing, XML, servlet,
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Performance Estimation at Architecture Level for Embedded Systems Hiroshi MIZUNO Hiroyuki KOBAYASHI Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2636-2644 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Performance Estimation Keyword: power dissipation, architecture, embedded system, co-design,
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Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol Yoshihiro OHTANI Nobuyuki KAWAHARA Hiroyuki NAKAOKA Tomonobu TOMARU Kazuhito MARUYAMA Toru CHIBA Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2002/10/01 Vol. E85-B No. 10 pp. 2032-2043 Type of Manuscript: Special Section PAPER (Special Issue on Mobile Multimedia Communications) Category: Keyword: wireless, video, hybrid ARQ, IEEE 802.11b, MPEG2,
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Error Detection by Digital Watermarking for MPEG-4 Video Coding Hiroyuki OKADA Altan-Erdene SHIITEV Hak-Sop SONG Gen FUJITA Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/06/01 Vol. E85-A No. 6 pp. 1281-1288 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2001 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2001)) Category: Keyword: MPEG-4, error resilience, error detection, digital watermarking,
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Code Efficiency Evaluation for Embedded Processors Morgan Hirosuke MIKI Mamoru SAKAMOTO Shingo MIYAMOTO Yoshinori TAKEUCHI Toyohiko YOSHIDA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 811-818 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: code efficiency, profiling, processor architecture,
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An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth Roberto Y. OMAKI Gen FUJITA Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/03/01 Vol. E85-A No. 3 pp. 703-713 Type of Manuscript: PAPER Category: Image Keyword: discrete wavelet transform, Embedded Zerotree Wavelet, video compression, VLSI,
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A 25 kV ESD Proof LDMOSFET with a Turn-on Discharge MOSFET Kazunori KAWAMOTO Kenji KOHNO Yasushi HIGUCHI Seiji FUJINO Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/06/01 Vol. E84-C No. 6 pp. 823-831 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: LDMOSFET, ESD, static discharge, thick SOI,
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3D Acoustic Image Localization Algorithm by Embedded DSP Wataru KOBAYASHI Noriaki SAKAMOTO Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/06/01 Vol. E84-A No. 6 pp. 1423-1430 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000)) Category: Keyword: 3D sound localization, HRTF, frequency division, DSP implementation, low computational costs,
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A 200 V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays Kazunori KAWAMOTO Hitoshi YAMAGUCHI Hiroaki HIMI Seiji FUJINO Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 260-266 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: high voltage CMOS, thick SOI, trench isolation, EL driver, LDMOS,
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Low-Power Scheme of NMOS 4-Phase Dynamic Logic Bao-Yu SONG Makoto FURUIE Yukihiro YOSHIDA Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 pp. 1772-1776 Type of Manuscript: Special Section LETTER (Special Issue on Integrated Electronics and New System Paradigms) Category: Low-Power Circuit Technique Keyword: low power, 4-phase dynamic logic, short-circuit current, small voltage swing,
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A Low-Power DSP Core Architecture for Low Bitrate Speech Codec Hiroyuki OKUHATA Morgan H. MIKI Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/08/25 Vol. E81-A No. 8 pp. 1616-1621 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: G. 723. 1, VLSI, DSP, low-power, speech codec,
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A VLSI Architecture for Motion Estimation Core Dedicated to H. 263 Video Coding Gen FUJITA Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 pp. 702-707 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: H. 263, VLSI, motion estimation, hierarchical search,
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A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells Itthichai ARUNGSRISANGCHAI Yuji SHIGEHIRO Isao SHIRAKAWA Hiromitsu TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/12/25 Vol. E80-A No. 12 pp. 2589-2599 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: VLSI, fabrication technology, mask pattern, LP, flow,
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A High Performance Multiplier and Its Application to an FlR Filter Dedicated to Digital Video Transmission Keisuke OKADA Shun MORIKAWA Sumitaka TAKEUCHI Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/25 Vol. E79-A No. 12 pp. 2106-2111 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: multiplier, constant coefficient, FIR filter, video transmission,
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Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP＠HL Takao ONOYE Gen FUJITA Masamichi TAKATSU Isao SHIRAKAWA Nariyoshi YAMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/08/25 Vol. E79-A No. 8 pp. 1210-1216 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: MPEG2, HDTV, VLSI, motion estimation,
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Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures Takao ONOYE Toshihiro MASAKI Yasuo MORIMOTO Yoh SATO Isao SHIRAKAWA Kenji MATSUMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/25 Vol. E79-A No. 3 pp. 330-338 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: MPEG2, HDTV, VLSI, decorder ASIC,
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High-Level Synthesis of a Multithreaded Processor for Image Generation Takao ONOYE Toshihiro MASAKI Isao SHIRAKAWA Hiroaki HIRATA Kozo KIMURA Shigeo ASAHARA Takayuki SAGISHIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/25 Vol. E78-A No. 3 pp. 322-330 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology and CAD Keyword: processor, multithread, parallel processing, high-level synthesis, image generation,
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Datapath Scheduling for Behavioral Description with Conditional Branches Akihisa YAMADA Toshiki YAMAZAKI Nagisa ISHIURA Isao SHIRAKAWA Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 pp. 1999-2009 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, datapath scheduling, 0-1 integer programming problem, binary decision diagram, branch-and-bound method,
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A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement Masahiko TOYONAGA Shih-Tsung YANG Isao SHIRAKAWA Toshiro AKINO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 pp. 2045-2052 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: clustering, fractal analysis, placement, partitioning,
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A Factored Reliability Formula for Directed Source-to-All-Terminal Networks Yoichi HIGASHIYAMA Hiromu ARIYOSHI Isao SHIRAKAWA Shogo OHBA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/01/25 Vol. E77-A No. 1 pp. 134-143 Type of Manuscript: Special Section PAPER (Special Section on Reliability) Category: System Reliability Keyword: source-to-all-terminal network reliability, factored formula, condensed graph, topological order of vertices,
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Test Generation for Sequential Circits Using Partitioned Image Computation Hoyong CHOI Hironori MAEDA Takashi KOHARA Nagisa ISHIURA Isao SHIRAKAWA Akira MOTOHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-A No. 10 pp. 1770-1774 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: test generation for sequential circuitt, product machine traversal method, mixed breadth-first/depth-first traversal, partitioned image computation,
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Research Topics and Results on Simulation for VLSI Isao SHIRAKAWA Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/07/25 Vol. E76-A No. 7 pp. 1070-1076 Type of Manuscript: Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I) Category: Keyword: VLSI, circuit simulation, logic simulation,
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A Recycling Scheme for Layout Patterns Used in an Old Fabrication Technology Yuji SHIGEHIRO Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/25 Vol. E76-A No. 6 pp. 886-893 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92)) Category: Algorithms for VLSI Design Keyword: VLSI, fabrication technology, mask pattern, layout description,
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A Distributed Routing System for Multilayer SOG Takashi SHIMAMOTO Isao SHIRAKAWA Hidetaka HANE Nobuyasu YUI Nobuyuki NISHIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/03/25 Vol. E76-A No. 3 pp. 370-376 Type of Manuscript: Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems) Category: Keyword: router, distribution, SOG, rip-up and reroute, variable-cost maze,
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An Automatic Layout Generator for Bipolar Analog Modules Takao ONOYE Akihisa YAMADA Itthichai ARUNGSRISANGCHAI Masakazu TANAKA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-A No. 10 pp. 1306-1314 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: layout generator, analog curcuit, one-dimensianal array, block compaction,
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An Extended Digital Fault Simulator for VLSI Circuits Min Sup KANG Hiroaki IWASHITA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/10/25 Vol. E74-A No. 10 pp. 3051-3056 Type of Manuscript: Special Section PAPER (Special Issue on JTC-CSCC '90) Category: VLSI Design Technology Keyword:
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An Efficient Heuristic Approach to State Encoding for PLA-Based Sequential Circuits Kenji MINATO Hiromu ARIYOSHI Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1991/01/25 Vol. E74-A No. 1 pp. 14-21 Type of Manuscript: INVITED PAPER Category: Keyword:
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FOREWORD Isao SHIRAKAWA Hiroki KUNIEDA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1988/12/25 Vol. E71-E No. 12 pp. 1176-1176 Type of Manuscript: FOREWORD Category: Keyword:
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On a Second Shortest k-Tuple of Edge-Disjoint Paths Shoji SHINODA Shuji TSUKIYAMA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS (1976-1990) Publication Date: 1987/10/25 Vol. E70-E No. 10 pp. 945-950 Type of Manuscript: PAPER Category: Graphs and Networks Keyword:
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