Ippei AKITA

A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique
Takayuki OKAZAWA Ippei AKITA 
Publication:   
Publication Date: 2018/05/01
Vol. E101-C  No. 5  pp. 396-403
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
dynamic latched comparator, self-calibrating, stochastic offset voltage detection, 
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A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS
Masanori FURUTA Ippei AKITA Junya MATSUNO Tetsuro ITAKURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7  pp. 1552-1561
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
time-interleaved, SAR, ADC, dynamic, T/H circuit, high-speed, low-power, 
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A 0.8-V Syllabic-Companding Log Domain Filter with 78-dB Dynamic Range in 0.35-µm CMOS
Ippei AKITA Kazuyuki WADA Yoshiaki TADOKORO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/01/01
Vol. E91-C  No. 1  pp. 87-95
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
low-supply voltage, analog filter, syllabic companding technique, log domain, dynamically adjustable biasing technique, 
 Summary | Full Text:PDF
Synthesis Method of All Low-Voltage CMOS Instantaneous-Companding Log Domain Integrators
Ippei AKITA Kazuyuki WADA Yoshiaki TADOKORO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/02/01
Vol. E90-A  No. 2  pp. 339-350
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
low-supply voltage, integrators, instantaneous companding, log domain, topological optimization, 
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