In-Cheol PARK


Low-Latency Low-Cost Architecture for Square and Cube Roots
Jihyuck JO In-Cheol PARK 
Publication:   
Publication Date: 2017/09/01
Vol. E100-A  No. 9  pp. 1951-1955
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
computer arithmeticcube rootssquare rootsnon-iterative root calculation
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Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems
Youngjoo LEE Jaehwan JUNG In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Vol. E99-C  No. 2  pp. 293-301
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
energy-efficient designforward error-correctionNAND flash memoryVLSI designs
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Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division
Bongjin KIM In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/07/01
Vol. E96-B  No. 7  pp. 1772-1779
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
low-density parity-check (LDPC) codesmulti-mode decoderlow-area architecturestride scheduling
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Efficient Pruning for Infinity-Norm Sphere Decoding Based on Schnorr-Euchner Enumeration
Tae-Hwan KIM In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/09/01
Vol. E94-B  No. 9  pp. 2677-2680
Type of Manuscript:  LETTER
Category: Wireless Communication Technologies
Keyword: 
multiple-input multiple-outputmaximum-likelihood detectionsphere decodingtree searchinfinity norm
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Multiplier-less and Table-less Linear Approximation for Square-Related Functions
In-Cheol PARK Tae-Hwan KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/11/01
Vol. E93-D  No. 11  pp. 2979-2988
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
squaresquare-rootinverse squareinverse square-rootcomputer arithmeticapproximationlinear interpolation
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Long-Point FFT Processing Based on Twiddle Factor Table Reduction
Ji-Hoon KIM In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/11/01
Vol. E90-A  No. 11  pp. 2526-2532
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
discrete Fourier transform (DFT)fast Fourier transform (FFT)low-power designorthogonal frequency division multiplexing (OFDM)pipelined processing
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Parallel Decoding of Context-Based Adaptive Binary Arithmetic Codes Based on Most Probable Symbol Prediction
Chung-Hyo KIM In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/02/01
Vol. E90-D  No. 2  pp. 609-612
Type of Manuscript:  LETTER
Category: Image Processing and Video Processing
Keyword: 
video codingarithmetic codesprediction theoryentropy codes
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Low-Power Hybrid Turbo Decoding Based on Reverse Calculation
Hye-Mi CHOI Ji-Hoon KIM In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/03/01
Vol. E89-A  No. 3  pp. 782-789
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
log-MAP algorithmlow-power designMax-log-MAP algorithmreverse calculationturbo codesturbo codingturbo decoding
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A Low-Complexity Stopping Criterion for Iterative Turbo Decoding
Dong-Soo LEE In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2005/01/01
Vol. E88-B  No. 1  pp. 399-401
Type of Manuscript:  LETTER
Category: Wireless Communication Technologies
Keyword: 
iterative decodingstopping criteriaturbo decoder
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An Area-Efficient and Fully Synthesizable Bluetooth Baseband Module for Wireless Communication
Ik-Jae CHUN Bo-Gwan KIM In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/01/01
Vol. E87-C  No. 1  pp. 94-100
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
Bluetoothbaseband modulewireless communicationIP
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An Automatic Interface Insertion Scheme for In-System Verification of Algorithm Models in C
Chang-Jae PARK Ando KI In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2645-2654
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High Level Synthesis
Keyword: 
automatic interface insertionin-system verificationsource-to-source translation
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Loop and Address Code Optimization for Digital Signal Processors
Jong-Yeol LEE In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6  pp. 1408-1415
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
digital signal processor (DSP)compilercode optimization
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Synthesis of Application-Specific Coprocessor for Core-Based ASIC Design
Dae-Hyun LEE In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Vol. E84-A  No. 2  pp. 604-613
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
core-based designhardware/software codesigncoprocessor
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CLASSIC: An O(n2)-Heuristic Algorithm for Microcode Bit Optimization Based on Incompleteness Relations
Young-doo CHOI In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/05/25
Vol. E83-A  No. 5  pp. 901-908
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
control memoryheuristic algorithminstruction memorymicroprogrammingminimization
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A New Single-Clock Flip-Flop for Half-Swing Clocking
Young-Su KWON In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2521-2526
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
low power circuitclocking powerhalf-swing clocking
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Improving Dictionary-Based Code Compression in VLIW Architectures
Sang-Joon NAM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2318-2324
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
code compressionVLIW architecture
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Path-Classified Trace Cache for Improving Hit Ratio in Wide-Issue Processors
Jin-Hyuk YANG In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/10/25
Vol. E82-D  No. 10  pp. 1338-1343
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
superscalarinstruction fetchtrace cache
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A Hierarchical Circuit Clustering Algorithm with Stable Performance
Seung-June KYOUNG Kwang-Su SEONG In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9  pp. 1987-1993
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
VLSICADpartitioningclustering
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Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors
Sang-Joon NAM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/03/25
Vol. E82-D  No. 3  pp. 645-653
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
computer architectureprecise interruptmultiple out-of-order issue processors
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SEWD: A Cache Architecture to Speed up the Misaligned Instruction Prefetch
Joon-Seo YIM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/07/25
Vol. E80-D  No. 7  pp. 742-745
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
cachemicroprocessorpipeline
 Summary | Full Text:PDF

Hardware Accelerator for Outline Font Generation
Gyu-Cheol HWANG In-Cheol PARK Yun-Tae LEE Tae-Hyung LEE Jong-Hong BAE Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/10/25
Vol. E74-A  No. 10  pp. 3078-3082
Type of Manuscript:  Special Section PAPER (Special Issue on JTC-CSCC '90)
Category: VLSI Design Technology
Keyword: 
 Summary | Full Text:PDF