A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA
Hui QIN Tsutomu SASAO Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1139-1147
Type of Manuscript:  PAPER
Category: Computer Components
AES encryptionpipelined partial rolling (PPR)FPGA
 Summary | Full Text:PDF(1.3MB)

A Realization of Multiple-Output Functions by a Look-Up Table Ring
Hui QIN Tsutomu SASAO Munehiro MATSUURA Shinobu NAGAYAMA Kazuyuki NAKAMURA Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3141-3150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
LUT cascadeLUT ringmultiple-output functionreconfigurable logicprogrammable logic device
 Summary | Full Text:PDF(675.1KB)